# # ChangeLog for trunk/Xilinx/cachedir.v in XOpenSparcT1 # # Generated by Trac 0.12.2 # 11/28/24 18:49:02 Tue, 05 Apr 2011 09:58:40 GMT pntsvt00 [27] * trunk/NOR-flash/WBFLASH.v (modified) * trunk/T1-common/srams/bw_r_scm.v (modified) * trunk/Top/W1.v (modified) * trunk/Xilinx/cachedir.v (modified) * trunk/os2wb/os2wb.v (modified) * trunk/sim/simula.do (modified) * trunk/sw/hello2.c (added) eliminato baco store consecutivi. esegue correttamente il codice Mon, 04 Apr 2011 11:58:11 GMT pntsvt00 [26] * trunk/T1-CPU/exu/sparc_exu.v (modified) * trunk/T1-CPU/exu/sparc_exu_alu.v (modified) * trunk/T1-common/srams/bw_r_irf.v (modified) * trunk/WB/wb_conbus_top.v (modified) * trunk/Xilinx/cachedir.v (modified) * trunk/os2wb/os2wb.v (modified) * trunk/sim/flash.v (modified) * trunk/sim/simula.do (modified) * trunk/sw/hello.c (modified) * trunk/sw/hello.dump (modified) * trunk/tools/dump2hex.php (modified) checkpoint: baco con store consecutivi Fri, 25 Mar 2011 12:19:25 GMT pntsvt00 [17] * trunk/Top/W1.v (modified) * trunk/WB/wb_conbus_top.v (modified) * trunk/WB2ALTDDR3/dram_wb.v (modified) * trunk/Xilinx/cachedir.v (modified) * trunk/Xilinx/dram.v (modified) * trunk/os2wb/os2wb.v (modified) * trunk/sim/flash.v (modified) * trunk/sim/simula.do (modified) * trunk/sim/tb_top.v (modified) * trunk/tools (added) * trunk/tools/dump2hex.php (added) la simulazione legge dalla flash Tue, 22 Mar 2011 20:08:58 GMT pntsvt00 [10] * README.TXT (added) * trunk/Top/W1.v (modified) * trunk/WB2ALTDDR3/dram_wb.v (modified) * trunk/Xilinx/cachedir.v (added) * trunk/Xilinx/ddr2_chipscope.v (added) * trunk/Xilinx/ddr2_ctrl.v (added) * trunk/Xilinx/ddr2_idelay_ctrl.v (added) * trunk/Xilinx/ddr2_infrastructure.v (added) * trunk/Xilinx/ddr2_mem_if_top.v (added) * trunk/Xilinx/ddr2_phy_calib.v (added) * trunk/Xilinx/ddr2_phy_ctl_io.v (added) * trunk/Xilinx/ddr2_phy_dm_iob.v (added) * trunk/Xilinx/ddr2_phy_dq_iob.v (added) * trunk/Xilinx/ddr2_phy_dqs_iob.v (added) * trunk/Xilinx/ddr2_phy_init.v (added) * trunk/Xilinx/ddr2_phy_io.v (added) * trunk/Xilinx/ddr2_phy_top.v (added) * trunk/Xilinx/ddr2_phy_write.v (added) * trunk/Xilinx/ddr2_top.v (added) * trunk/Xilinx/ddr2_usr_addr_fifo.v (added) * trunk/Xilinx/ddr2_usr_rd.v (added) * trunk/Xilinx/ddr2_usr_top.v (added) * trunk/Xilinx/ddr2_usr_wr.v (added) * trunk/Xilinx/dram.v (added) * trunk/Xilinx/pll.v (modified) * trunk/os2wb/os2wb.v (modified) * trunk/os2wb/s1_top.v (modified) * trunk/sim (added) * trunk/sim/ddr2_model.v (added) * trunk/sim/ddr2_model_parameters.vh (added) * trunk/sim/sim.do (added) * trunk/sim/sim_tb_top.v (added) * trunk/sim/sim_tb_top.vhd (added) * trunk/sim/wiredly.v (added) * trunk/sim/wiredly.vhd (added) * trunk/synplicity/proj_1.prj (modified) * trunk/synplicity/rev_1/W1.ucf (added) * trunk/synplicity/rev_1/dram_fifo.ngc (added) * trunk/synplicity/rev_1/pcx_fifo.ngc (added) * trunk/synplicity/rev_1/run_ise.tcl (added) * trunk/synplicity/rev_1/run_xise.tcl (added) * trunk/synplicity/rev_1/synplicity.ucf (added) versione sintetizzabile