source: XOpenSparcT1/trunk/synplicity/rev_1/run_xise.tcl @ 9

Revision 9, 852 bytes checked in by pntsvt00, 14 years ago (diff)

modifiche per la sintesi su Xilinx

RevLine 
[9]1#########################
2###  DEFINE VARIABLES ###
3#########################
4set DesignName  "W1"
5set FamilyName  "VIRTEX5"
6set DeviceName  "XC5VLX110T"
7set PackageName "FF1136"
8set SpeedGrade  "-1"
9set TopModule   "W1"
10set EdifFile    "W1.edf"
11if {![file exists $DesignName.xise]} {
12
13project new $DesignName.xise
14
15project set family $FamilyName
16project set device $DeviceName
17project set package $PackageName
18project set speed $SpeedGrade
19
20xfile add W1.ucf
21#xfile add $EdifFile
22#if {[file exists synplicity.ucf]} {
23#    xfile add synplicity.ucf
24#}
25
26project set "Netlist Translation Type" "Timestamp"
27project set "Other NGDBuild Command Line Options" "-verbose"
28project set "Generate Detailed MAP Report" TRUE
29
30project close
31}
32
33
34file delete -force $DesignName\_xdb
35
36project open $DesignName.ise
37
38process run "Implement Design" -force rerun_all
39
40project close
41
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