| [6] | 1 | ////////////////////////////////////////////////////////////////////// |
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| 2 | //// //// |
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| 3 | //// uart_transmitter.v //// |
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| 4 | //// //// |
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| 5 | //// //// |
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| 6 | //// This file is part of the "UART 16550 compatible" project //// |
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| 7 | //// http://www.opencores.org/cores/uart16550/ //// |
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| 8 | //// //// |
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| 9 | //// Documentation related to this project: //// |
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| 10 | //// - http://www.opencores.org/cores/uart16550/ //// |
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| 11 | //// //// |
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| 12 | //// Projects compatibility: //// |
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| 13 | //// - WISHBONE //// |
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| 14 | //// RS232 Protocol //// |
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| 15 | //// 16550D uart (mostly supported) //// |
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| 16 | //// //// |
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| 17 | //// Overview (main Features): //// |
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| 18 | //// UART core transmitter logic //// |
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| 19 | //// //// |
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| 20 | //// Known problems (limits): //// |
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| 21 | //// None known //// |
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| 22 | //// //// |
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| 23 | //// To Do: //// |
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| 24 | //// Thourough testing. //// |
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| 25 | //// //// |
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| 26 | //// Author(s): //// |
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| 27 | //// - [email protected] //// |
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| 28 | //// - Jacob Gorban //// |
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| 29 | //// - Igor Mohor ([email protected]) //// |
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| 30 | //// //// |
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| 31 | //// Created: 2001/05/12 //// |
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| 32 | //// Last Updated: 2001/05/17 //// |
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| 33 | //// (See log for the revision history) //// |
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| 34 | //// //// |
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| 35 | //// //// |
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| 36 | ////////////////////////////////////////////////////////////////////// |
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| 37 | //// //// |
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| 38 | //// Copyright (C) 2000, 2001 Authors //// |
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| 39 | //// //// |
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| 40 | //// This source file may be used and distributed without //// |
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| 41 | //// restriction provided that this copyright statement is not //// |
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| 42 | //// removed from the file and that any derivative work contains //// |
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| 43 | //// the original copyright notice and the associated disclaimer. //// |
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| 44 | //// //// |
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| 45 | //// This source file is free software; you can redistribute it //// |
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| 46 | //// and/or modify it under the terms of the GNU Lesser General //// |
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| 47 | //// Public License as published by the Free Software Foundation; //// |
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| 48 | //// either version 2.1 of the License, or (at your option) any //// |
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| 49 | //// later version. //// |
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| 50 | //// //// |
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| 51 | //// This source is distributed in the hope that it will be //// |
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| 52 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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| 53 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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| 54 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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| 55 | //// details. //// |
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| 56 | //// //// |
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| 57 | //// You should have received a copy of the GNU Lesser General //// |
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| 58 | //// Public License along with this source; if not, download it //// |
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| 59 | //// from http://www.opencores.org/lgpl.shtml //// |
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| 60 | //// //// |
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| 61 | ////////////////////////////////////////////////////////////////////// |
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| 62 | // |
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| 63 | // CVS Revision History |
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| 64 | // |
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| 65 | // $Log: not supported by cvs2svn $ |
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| 66 | // Revision 1.18 2002/07/22 23:02:23 gorban |
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| 67 | // Bug Fixes: |
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| 68 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
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| 69 | // Problem reported by Kenny.Tung. |
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| 70 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
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| 71 | // |
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| 72 | // Improvements: |
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| 73 | // * Made FIFO's as general inferrable memory where possible. |
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| 74 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
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| 75 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
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| 76 | // |
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| 77 | // * Added optional baudrate output (baud_o). |
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| 78 | // This is identical to BAUDOUT* signal on 16550 chip. |
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| 79 | // It outputs 16xbit_clock_rate - the divided clock. |
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| 80 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
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| 81 | // |
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| 82 | // Revision 1.16 2002/01/08 11:29:40 mohor |
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| 83 | // tf_pop was too wide. Now it is only 1 clk cycle width. |
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| 84 | // |
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| 85 | // Revision 1.15 2001/12/17 14:46:48 mohor |
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| 86 | // overrun signal was moved to separate block because many sequential lsr |
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| 87 | // reads were preventing data from being written to rx fifo. |
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| 88 | // underrun signal was not used and was removed from the project. |
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| 89 | // |
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| 90 | // Revision 1.14 2001/12/03 21:44:29 gorban |
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| 91 | // Updated specification documentation. |
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| 92 | // Added full 32-bit data bus interface, now as default. |
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| 93 | // Address is 5-bit wide in 32-bit data bus mode. |
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| 94 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. |
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| 95 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. |
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| 96 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. |
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| 97 | // My small test bench is modified to work with 32-bit mode. |
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| 98 | // |
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| 99 | // Revision 1.13 2001/11/08 14:54:23 mohor |
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| 100 | // Comments in Slovene language deleted, few small fixes for better work of |
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| 101 | // old tools. IRQs need to be fix. |
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| 102 | // |
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| 103 | // Revision 1.12 2001/11/07 17:51:52 gorban |
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| 104 | // Heavily rewritten interrupt and LSR subsystems. |
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| 105 | // Many bugs hopefully squashed. |
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| 106 | // |
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| 107 | // Revision 1.11 2001/10/29 17:00:46 gorban |
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| 108 | // fixed parity sending and tx_fifo resets over- and underrun |
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| 109 | // |
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| 110 | // Revision 1.10 2001/10/20 09:58:40 gorban |
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| 111 | // Small synopsis fixes |
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| 112 | // |
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| 113 | // Revision 1.9 2001/08/24 21:01:12 mohor |
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| 114 | // Things connected to parity changed. |
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| 115 | // Clock devider changed. |
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| 116 | // |
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| 117 | // Revision 1.8 2001/08/23 16:05:05 mohor |
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| 118 | // Stop bit bug fixed. |
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| 119 | // Parity bug fixed. |
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| 120 | // WISHBONE read cycle bug fixed, |
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| 121 | // OE indicator (Overrun Error) bug fixed. |
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| 122 | // PE indicator (Parity Error) bug fixed. |
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| 123 | // Register read bug fixed. |
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| 124 | // |
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| 125 | // Revision 1.6 2001/06/23 11:21:48 gorban |
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| 126 | // DL made 16-bit long. Fixed transmission/reception bugs. |
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| 127 | // |
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| 128 | // Revision 1.5 2001/06/02 14:28:14 gorban |
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| 129 | // Fixed receiver and transmitter. Major bug fixed. |
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| 130 | // |
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| 131 | // Revision 1.4 2001/05/31 20:08:01 gorban |
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| 132 | // FIFO changes and other corrections. |
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| 133 | // |
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| 134 | // Revision 1.3 2001/05/27 17:37:49 gorban |
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| 135 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. |
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| 136 | // |
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| 137 | // Revision 1.2 2001/05/21 19:12:02 gorban |
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| 138 | // Corrected some Linter messages. |
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| 139 | // |
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| 140 | // Revision 1.1 2001/05/17 18:34:18 gorban |
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| 141 | // First 'stable' release. Should be sythesizable now. Also added new header. |
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| 142 | // |
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| 143 | // Revision 1.0 2001-05-17 21:27:12+02 jacob |
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| 144 | // Initial revision |
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| 145 | // |
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| 146 | // |
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| 147 | |
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| 148 | // synopsys translate_off |
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| 149 | `include "timescale.v" |
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| 150 | // synopsys translate_on |
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| 151 | |
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| 152 | `include "uart_defines.v" |
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| 153 | |
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| 154 | module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); |
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| 155 | |
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| 156 | input clk; |
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| 157 | input wb_rst_i; |
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| 158 | input [7:0] lcr; |
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| 159 | input tf_push; |
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| 160 | input [7:0] wb_dat_i; |
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| 161 | input enable; |
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| 162 | input tx_reset; |
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| 163 | input lsr_mask; //reset of fifo |
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| 164 | output stx_pad_o; |
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| 165 | output [2:0] tstate; |
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| 166 | output [`UART_FIFO_COUNTER_W-1:0] tf_count; |
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| 167 | |
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| 168 | reg [2:0] tstate; |
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| 169 | reg [4:0] counter; |
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| 170 | reg [2:0] bit_counter; // counts the bits to be sent |
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| 171 | reg [6:0] shift_out; // output shift register |
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| 172 | reg stx_o_tmp; |
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| 173 | reg parity_xor; // parity of the word |
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| 174 | reg tf_pop; |
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| 175 | reg bit_out; |
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| 176 | |
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| 177 | // TX FIFO instance |
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| 178 | // |
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| 179 | // Transmitter FIFO signals |
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| 180 | wire [`UART_FIFO_WIDTH-1:0] tf_data_in; |
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| 181 | wire [`UART_FIFO_WIDTH-1:0] tf_data_out; |
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| 182 | wire tf_push; |
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| 183 | wire tf_overrun; |
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| 184 | wire [`UART_FIFO_COUNTER_W-1:0] tf_count; |
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| 185 | |
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| 186 | assign tf_data_in = wb_dat_i; |
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| 187 | |
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| 188 | uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO |
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| 189 | .clk( clk ), |
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| 190 | .wb_rst_i( wb_rst_i ), |
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| 191 | .data_in( tf_data_in ), |
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| 192 | .data_out( tf_data_out ), |
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| 193 | .push( tf_push ), |
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| 194 | .pop( tf_pop ), |
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| 195 | .overrun( tf_overrun ), |
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| 196 | .count( tf_count ), |
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| 197 | .fifo_reset( tx_reset ), |
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| 198 | .reset_status(lsr_mask) |
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| 199 | ); |
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| 200 | |
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| 201 | // TRANSMITTER FINAL STATE MACHINE |
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| 202 | |
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| 203 | parameter s_idle = 3'd0; |
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| 204 | parameter s_send_start = 3'd1; |
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| 205 | parameter s_send_byte = 3'd2; |
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| 206 | parameter s_send_parity = 3'd3; |
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| 207 | parameter s_send_stop = 3'd4; |
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| 208 | parameter s_pop_byte = 3'd5; |
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| 209 | |
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| 210 | always @(posedge clk or posedge wb_rst_i) |
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| 211 | begin |
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| 212 | if (wb_rst_i) |
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| 213 | begin |
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| 214 | tstate <= #1 s_idle; |
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| 215 | stx_o_tmp <= #1 1'b1; |
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| 216 | counter <= #1 5'b0; |
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| 217 | shift_out <= #1 7'b0; |
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| 218 | bit_out <= #1 1'b0; |
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| 219 | parity_xor <= #1 1'b0; |
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| 220 | tf_pop <= #1 1'b0; |
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| 221 | bit_counter <= #1 3'b0; |
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| 222 | end |
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| 223 | else |
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| 224 | if (enable) |
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| 225 | begin |
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| 226 | case (tstate) |
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| 227 | s_idle : if (~|tf_count) // if tf_count==0 |
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| 228 | begin |
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| 229 | tstate <= #1 s_idle; |
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| 230 | stx_o_tmp <= #1 1'b1; |
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| 231 | end |
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| 232 | else |
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| 233 | begin |
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| 234 | tf_pop <= #1 1'b0; |
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| 235 | stx_o_tmp <= #1 1'b1; |
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| 236 | tstate <= #1 s_pop_byte; |
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| 237 | end |
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| 238 | s_pop_byte : begin |
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| 239 | tf_pop <= #1 1'b1; |
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| 240 | case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
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| 241 | 2'b00 : begin |
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| 242 | bit_counter <= #1 3'b100; |
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| 243 | parity_xor <= #1 ^tf_data_out[4:0]; |
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| 244 | end |
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| 245 | 2'b01 : begin |
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| 246 | bit_counter <= #1 3'b101; |
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| 247 | parity_xor <= #1 ^tf_data_out[5:0]; |
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| 248 | end |
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| 249 | 2'b10 : begin |
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| 250 | bit_counter <= #1 3'b110; |
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| 251 | parity_xor <= #1 ^tf_data_out[6:0]; |
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| 252 | end |
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| 253 | 2'b11 : begin |
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| 254 | bit_counter <= #1 3'b111; |
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| 255 | parity_xor <= #1 ^tf_data_out[7:0]; |
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| 256 | end |
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| 257 | endcase |
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| 258 | {shift_out[6:0], bit_out} <= #1 tf_data_out; |
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| 259 | tstate <= #1 s_send_start; |
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| 260 | end |
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| 261 | s_send_start : begin |
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| 262 | tf_pop <= #1 1'b0; |
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| 263 | if (~|counter) |
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| 264 | counter <= #1 5'b01111; |
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| 265 | else |
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| 266 | if (counter == 5'b00001) |
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| 267 | begin |
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| 268 | counter <= #1 0; |
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| 269 | tstate <= #1 s_send_byte; |
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| 270 | end |
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| 271 | else |
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| 272 | counter <= #1 counter - 1'b1; |
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| 273 | stx_o_tmp <= #1 1'b0; |
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| 274 | end |
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| 275 | s_send_byte : begin |
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| 276 | if (~|counter) |
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| 277 | counter <= #1 5'b01111; |
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| 278 | else |
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| 279 | if (counter == 5'b00001) |
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| 280 | begin |
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| 281 | if (bit_counter > 3'b0) |
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| 282 | begin |
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| 283 | bit_counter <= #1 bit_counter - 1'b1; |
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| 284 | {shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]}; |
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| 285 | tstate <= #1 s_send_byte; |
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| 286 | end |
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| 287 | else // end of byte |
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| 288 | if (~lcr[`UART_LC_PE]) |
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| 289 | begin |
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| 290 | tstate <= #1 s_send_stop; |
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| 291 | end |
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| 292 | else |
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| 293 | begin |
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| 294 | case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) |
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| 295 | 2'b00: bit_out <= #1 ~parity_xor; |
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| 296 | 2'b01: bit_out <= #1 1'b1; |
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| 297 | 2'b10: bit_out <= #1 parity_xor; |
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| 298 | 2'b11: bit_out <= #1 1'b0; |
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| 299 | endcase |
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| 300 | tstate <= #1 s_send_parity; |
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| 301 | end |
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| 302 | counter <= #1 0; |
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| 303 | end |
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| 304 | else |
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| 305 | counter <= #1 counter - 1'b1; |
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| 306 | stx_o_tmp <= #1 bit_out; // set output pin |
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| 307 | end |
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| 308 | s_send_parity : begin |
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| 309 | if (~|counter) |
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| 310 | counter <= #1 5'b01111; |
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| 311 | else |
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| 312 | if (counter == 5'b00001) |
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| 313 | begin |
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| 314 | counter <= #1 4'b0; |
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| 315 | tstate <= #1 s_send_stop; |
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| 316 | end |
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| 317 | else |
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| 318 | counter <= #1 counter - 1'b1; |
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| 319 | stx_o_tmp <= #1 bit_out; |
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| 320 | end |
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| 321 | s_send_stop : begin |
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| 322 | if (~|counter) |
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| 323 | begin |
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| 324 | casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) |
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| 325 | 3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor |
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| 326 | 3'b100: counter <= #1 5'b10101; // 1.5 stop bit |
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| 327 | default: counter <= #1 5'b11101; // 2 stop bits |
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| 328 | endcase |
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| 329 | end |
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| 330 | else |
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| 331 | if (counter == 5'b00001) |
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| 332 | begin |
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| 333 | counter <= #1 0; |
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| 334 | tstate <= #1 s_idle; |
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| 335 | end |
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| 336 | else |
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| 337 | counter <= #1 counter - 1'b1; |
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| 338 | stx_o_tmp <= #1 1'b1; |
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| 339 | end |
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| 340 | |
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| 341 | default : // should never get here |
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| 342 | tstate <= #1 s_idle; |
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| 343 | endcase |
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| 344 | end // end if enable |
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| 345 | else |
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| 346 | tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width |
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| 347 | end // transmitter logic |
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| 348 | |
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| 349 | assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition |
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| 350 | |
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| 351 | endmodule |
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