[6] | 1 | ////////////////////////////////////////////////////////////////////// |
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| 2 | //// //// |
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| 3 | //// uart_regs.v //// |
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| 4 | //// //// |
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| 5 | //// //// |
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| 6 | //// This file is part of the "UART 16550 compatible" project //// |
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| 7 | //// http://www.opencores.org/cores/uart16550/ //// |
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| 8 | //// //// |
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| 9 | //// Documentation related to this project: //// |
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| 10 | //// - http://www.opencores.org/cores/uart16550/ //// |
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| 11 | //// //// |
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| 12 | //// Projects compatibility: //// |
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| 13 | //// - WISHBONE //// |
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| 14 | //// RS232 Protocol //// |
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| 15 | //// 16550D uart (mostly supported) //// |
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| 16 | //// //// |
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| 17 | //// Overview (main Features): //// |
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| 18 | //// Registers of the uart 16550 core //// |
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| 19 | //// //// |
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| 20 | //// Known problems (limits): //// |
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| 21 | //// Inserts 1 wait state in all WISHBONE transfers //// |
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| 22 | //// //// |
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| 23 | //// To Do: //// |
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| 24 | //// Nothing or verification. //// |
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| 25 | //// //// |
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| 26 | //// Author(s): //// |
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| 27 | //// - [email protected] //// |
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| 28 | //// - Jacob Gorban //// |
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| 29 | //// - Igor Mohor ([email protected]) //// |
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| 30 | //// //// |
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| 31 | //// Created: 2001/05/12 //// |
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| 32 | //// Last Updated: (See log for the revision history //// |
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| 33 | //// //// |
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| 34 | //// //// |
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| 35 | ////////////////////////////////////////////////////////////////////// |
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| 36 | //// //// |
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| 37 | //// Copyright (C) 2000, 2001 Authors //// |
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| 38 | //// //// |
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| 39 | //// This source file may be used and distributed without //// |
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| 40 | //// restriction provided that this copyright statement is not //// |
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| 41 | //// removed from the file and that any derivative work contains //// |
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| 42 | //// the original copyright notice and the associated disclaimer. //// |
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| 43 | //// //// |
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| 44 | //// This source file is free software; you can redistribute it //// |
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| 45 | //// and/or modify it under the terms of the GNU Lesser General //// |
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| 46 | //// Public License as published by the Free Software Foundation; //// |
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| 47 | //// either version 2.1 of the License, or (at your option) any //// |
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| 48 | //// later version. //// |
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| 49 | //// //// |
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| 50 | //// This source is distributed in the hope that it will be //// |
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| 51 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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| 52 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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| 53 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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| 54 | //// details. //// |
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| 55 | //// //// |
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| 56 | //// You should have received a copy of the GNU Lesser General //// |
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| 57 | //// Public License along with this source; if not, download it //// |
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| 58 | //// from http://www.opencores.org/lgpl.shtml //// |
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| 59 | //// //// |
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| 60 | ////////////////////////////////////////////////////////////////////// |
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| 61 | // |
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| 62 | // CVS Revision History |
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| 63 | // |
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| 64 | // $Log: not supported by cvs2svn $ |
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| 65 | // Revision 1.41 2004/05/21 11:44:41 tadejm |
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| 66 | // Added synchronizer flops for RX input. |
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| 67 | // |
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| 68 | // Revision 1.40 2003/06/11 16:37:47 gorban |
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| 69 | // This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. |
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| 70 | // |
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| 71 | // Revision 1.39 2002/07/29 21:16:18 gorban |
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| 72 | // The uart_defines.v file is included again in sources. |
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| 73 | // |
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| 74 | // Revision 1.38 2002/07/22 23:02:23 gorban |
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| 75 | // Bug Fixes: |
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| 76 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
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| 77 | // Problem reported by Kenny.Tung. |
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| 78 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
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| 79 | // |
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| 80 | // Improvements: |
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| 81 | // * Made FIFO's as general inferrable memory where possible. |
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| 82 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
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| 83 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
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| 84 | // |
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| 85 | // * Added optional baudrate output (baud_o). |
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| 86 | // This is identical to BAUDOUT* signal on 16550 chip. |
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| 87 | // It outputs 16xbit_clock_rate - the divided clock. |
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| 88 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
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| 89 | // |
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| 90 | // Revision 1.37 2001/12/27 13:24:09 mohor |
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| 91 | // lsr[7] was not showing overrun errors. |
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| 92 | // |
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| 93 | // Revision 1.36 2001/12/20 13:25:46 mohor |
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| 94 | // rx push changed to be only one cycle wide. |
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| 95 | // |
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| 96 | // Revision 1.35 2001/12/19 08:03:34 mohor |
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| 97 | // Warnings cleared. |
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| 98 | // |
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| 99 | // Revision 1.34 2001/12/19 07:33:54 mohor |
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| 100 | // Synplicity was having troubles with the comment. |
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| 101 | // |
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| 102 | // Revision 1.33 2001/12/17 10:14:43 mohor |
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| 103 | // Things related to msr register changed. After THRE IRQ occurs, and one |
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| 104 | // character is written to the transmit fifo, the detection of the THRE bit in the |
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| 105 | // LSR is delayed for one character time. |
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| 106 | // |
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| 107 | // Revision 1.32 2001/12/14 13:19:24 mohor |
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| 108 | // MSR register fixed. |
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| 109 | // |
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| 110 | // Revision 1.31 2001/12/14 10:06:58 mohor |
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| 111 | // After reset modem status register MSR should be reset. |
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| 112 | // |
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| 113 | // Revision 1.30 2001/12/13 10:09:13 mohor |
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| 114 | // thre irq should be cleared only when being source of interrupt. |
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| 115 | // |
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| 116 | // Revision 1.29 2001/12/12 09:05:46 mohor |
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| 117 | // LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). |
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| 118 | // |
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| 119 | // Revision 1.28 2001/12/10 19:52:41 gorban |
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| 120 | // Scratch register added |
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| 121 | // |
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| 122 | // Revision 1.27 2001/12/06 14:51:04 gorban |
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| 123 | // Bug in LSR[0] is fixed. |
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| 124 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. |
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| 125 | // |
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| 126 | // Revision 1.26 2001/12/03 21:44:29 gorban |
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| 127 | // Updated specification documentation. |
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| 128 | // Added full 32-bit data bus interface, now as default. |
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| 129 | // Address is 5-bit wide in 32-bit data bus mode. |
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| 130 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. |
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| 131 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. |
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| 132 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. |
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| 133 | // My small test bench is modified to work with 32-bit mode. |
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| 134 | // |
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| 135 | // Revision 1.25 2001/11/28 19:36:39 gorban |
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| 136 | // Fixed: timeout and break didn't pay attention to current data format when counting time |
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| 137 | // |
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| 138 | // Revision 1.24 2001/11/26 21:38:54 gorban |
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| 139 | // Lots of fixes: |
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| 140 | // Break condition wasn't handled correctly at all. |
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| 141 | // LSR bits could lose their values. |
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| 142 | // LSR value after reset was wrong. |
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| 143 | // Timing of THRE interrupt signal corrected. |
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| 144 | // LSR bit 0 timing corrected. |
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| 145 | // |
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| 146 | // Revision 1.23 2001/11/12 21:57:29 gorban |
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| 147 | // fixed more typo bugs |
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| 148 | // |
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| 149 | // Revision 1.22 2001/11/12 15:02:28 mohor |
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| 150 | // lsr1r error fixed. |
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| 151 | // |
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| 152 | // Revision 1.21 2001/11/12 14:57:27 mohor |
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| 153 | // ti_int_pnd error fixed. |
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| 154 | // |
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| 155 | // Revision 1.20 2001/11/12 14:50:27 mohor |
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| 156 | // ti_int_d error fixed. |
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| 157 | // |
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| 158 | // Revision 1.19 2001/11/10 12:43:21 gorban |
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| 159 | // Logic Synthesis bugs fixed. Some other minor changes |
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| 160 | // |
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| 161 | // Revision 1.18 2001/11/08 14:54:23 mohor |
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| 162 | // Comments in Slovene language deleted, few small fixes for better work of |
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| 163 | // old tools. IRQs need to be fix. |
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| 164 | // |
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| 165 | // Revision 1.17 2001/11/07 17:51:52 gorban |
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| 166 | // Heavily rewritten interrupt and LSR subsystems. |
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| 167 | // Many bugs hopefully squashed. |
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| 168 | // |
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| 169 | // Revision 1.16 2001/11/02 09:55:16 mohor |
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| 170 | // no message |
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| 171 | // |
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| 172 | // Revision 1.15 2001/10/31 15:19:22 gorban |
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| 173 | // Fixes to break and timeout conditions |
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| 174 | // |
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| 175 | // Revision 1.14 2001/10/29 17:00:46 gorban |
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| 176 | // fixed parity sending and tx_fifo resets over- and underrun |
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| 177 | // |
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| 178 | // Revision 1.13 2001/10/20 09:58:40 gorban |
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| 179 | // Small synopsis fixes |
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| 180 | // |
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| 181 | // Revision 1.12 2001/10/19 16:21:40 gorban |
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| 182 | // Changes data_out to be synchronous again as it should have been. |
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| 183 | // |
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| 184 | // Revision 1.11 2001/10/18 20:35:45 gorban |
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| 185 | // small fix |
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| 186 | // |
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| 187 | // Revision 1.10 2001/08/24 21:01:12 mohor |
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| 188 | // Things connected to parity changed. |
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| 189 | // Clock devider changed. |
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| 190 | // |
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| 191 | // Revision 1.9 2001/08/23 16:05:05 mohor |
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| 192 | // Stop bit bug fixed. |
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| 193 | // Parity bug fixed. |
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| 194 | // WISHBONE read cycle bug fixed, |
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| 195 | // OE indicator (Overrun Error) bug fixed. |
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| 196 | // PE indicator (Parity Error) bug fixed. |
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| 197 | // Register read bug fixed. |
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| 198 | // |
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| 199 | // Revision 1.10 2001/06/23 11:21:48 gorban |
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| 200 | // DL made 16-bit long. Fixed transmission/reception bugs. |
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| 201 | // |
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| 202 | // Revision 1.9 2001/05/31 20:08:01 gorban |
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| 203 | // FIFO changes and other corrections. |
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| 204 | // |
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| 205 | // Revision 1.8 2001/05/29 20:05:04 gorban |
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| 206 | // Fixed some bugs and synthesis problems. |
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| 207 | // |
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| 208 | // Revision 1.7 2001/05/27 17:37:49 gorban |
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| 209 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. |
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| 210 | // |
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| 211 | // Revision 1.6 2001/05/21 19:12:02 gorban |
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| 212 | // Corrected some Linter messages. |
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| 213 | // |
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| 214 | // Revision 1.5 2001/05/17 18:34:18 gorban |
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| 215 | // First 'stable' release. Should be sythesizable now. Also added new header. |
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| 216 | // |
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| 217 | // Revision 1.0 2001-05-17 21:27:11+02 jacob |
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| 218 | // Initial revision |
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| 219 | // |
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| 220 | // |
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| 221 | |
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| 222 | // synopsys translate_off |
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| 223 | `include "timescale.v" |
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| 224 | // synopsys translate_on |
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| 225 | |
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| 226 | `include "uart_defines.v" |
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| 227 | |
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| 228 | `define UART_DL1 7:0 |
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| 229 | `define UART_DL2 15:8 |
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| 230 | |
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| 231 | module uart_regs (clk, |
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| 232 | wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i, |
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| 233 | |
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| 234 | // additional signals |
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| 235 | modem_inputs, |
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| 236 | stx_pad_o, srx_pad_i, |
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| 237 | |
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| 238 | `ifdef DATA_BUS_WIDTH_8 |
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| 239 | `else |
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| 240 | // debug interface signals enabled |
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| 241 | ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate, |
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| 242 | `endif |
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| 243 | rts_pad_o, dtr_pad_o, int_o |
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| 244 | `ifdef UART_HAS_BAUDRATE_OUTPUT |
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| 245 | , baud_o |
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| 246 | `endif |
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| 247 | |
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| 248 | ); |
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| 249 | |
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| 250 | input clk; |
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| 251 | input wb_rst_i; |
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| 252 | input [`UART_ADDR_WIDTH-1:0] wb_addr_i; |
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| 253 | input [7:0] wb_dat_i; |
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| 254 | output [7:0] wb_dat_o; |
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| 255 | input wb_we_i; |
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| 256 | input wb_re_i; |
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| 257 | |
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| 258 | output stx_pad_o; |
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| 259 | input srx_pad_i; |
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| 260 | |
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| 261 | input [3:0] modem_inputs; |
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| 262 | output rts_pad_o; |
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| 263 | output dtr_pad_o; |
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| 264 | output int_o; |
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| 265 | `ifdef UART_HAS_BAUDRATE_OUTPUT |
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| 266 | output baud_o; |
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| 267 | `endif |
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| 268 | |
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| 269 | `ifdef DATA_BUS_WIDTH_8 |
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| 270 | `else |
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| 271 | // if 32-bit databus and debug interface are enabled |
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| 272 | output [3:0] ier; |
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| 273 | output [3:0] iir; |
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| 274 | output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored |
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| 275 | output [4:0] mcr; |
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| 276 | output [7:0] lcr; |
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| 277 | output [7:0] msr; |
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| 278 | output [7:0] lsr; |
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| 279 | output [`UART_FIFO_COUNTER_W-1:0] rf_count; |
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| 280 | output [`UART_FIFO_COUNTER_W-1:0] tf_count; |
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| 281 | output [2:0] tstate; |
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| 282 | output [3:0] rstate; |
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| 283 | |
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| 284 | `endif |
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| 285 | |
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| 286 | wire [3:0] modem_inputs; |
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| 287 | reg enable; |
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| 288 | `ifdef UART_HAS_BAUDRATE_OUTPUT |
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| 289 | assign baud_o = enable; // baud_o is actually the enable signal |
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| 290 | `endif |
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| 291 | |
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| 292 | |
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| 293 | wire stx_pad_o; // received from transmitter module |
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| 294 | wire srx_pad_i; |
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| 295 | wire srx_pad; |
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| 296 | |
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| 297 | reg [7:0] wb_dat_o; |
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| 298 | |
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| 299 | wire [`UART_ADDR_WIDTH-1:0] wb_addr_i; |
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| 300 | wire [7:0] wb_dat_i; |
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| 301 | |
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| 302 | |
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| 303 | reg [3:0] ier; |
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| 304 | reg [3:0] iir; |
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| 305 | reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored |
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| 306 | reg [4:0] mcr; |
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| 307 | reg [7:0] lcr; |
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| 308 | reg [7:0] msr; |
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| 309 | reg [15:0] dl; // 32-bit divisor latch |
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| 310 | reg [7:0] scratch; // UART scratch register |
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| 311 | reg start_dlc; // activate dlc on writing to UART_DL1 |
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| 312 | reg lsr_mask_d; // delay for lsr_mask condition |
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| 313 | reg msi_reset; // reset MSR 4 lower bits indicator |
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| 314 | //reg threi_clear; // THRE interrupt clear flag |
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| 315 | reg [15:0] dlc; // 32-bit divisor latch counter |
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| 316 | reg int_o; |
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| 317 | |
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| 318 | reg [3:0] trigger_level; // trigger level of the receiver FIFO |
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| 319 | reg rx_reset; |
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| 320 | reg tx_reset; |
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| 321 | |
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| 322 | wire dlab; // divisor latch access bit |
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| 323 | wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits |
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| 324 | wire loopback; // loopback bit (MCR bit 4) |
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| 325 | wire cts, dsr, ri, dcd; // effective signals |
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| 326 | wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback) |
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| 327 | wire rts_pad_o, dtr_pad_o; // modem control outputs |
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| 328 | |
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| 329 | // LSR bits wires and regs |
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| 330 | wire [7:0] lsr; |
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| 331 | wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; |
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| 332 | reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; |
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| 333 | wire lsr_mask; // lsr_mask |
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| 334 | |
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| 335 | // |
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| 336 | // ASSINGS |
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| 337 | // |
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| 338 | |
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| 339 | assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; |
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| 340 | |
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| 341 | assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; |
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| 342 | assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; |
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| 343 | |
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| 344 | assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} |
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| 345 | : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; |
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| 346 | |
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| 347 | assign dlab = lcr[`UART_LC_DL]; |
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| 348 | assign loopback = mcr[4]; |
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| 349 | |
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| 350 | // assign modem outputs |
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| 351 | assign rts_pad_o = mcr[`UART_MC_RTS]; |
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| 352 | assign dtr_pad_o = mcr[`UART_MC_DTR]; |
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| 353 | |
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| 354 | // Interrupt signals |
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| 355 | wire rls_int; // receiver line status interrupt |
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| 356 | wire rda_int; // receiver data available interrupt |
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| 357 | wire ti_int; // timeout indicator interrupt |
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| 358 | wire thre_int; // transmitter holding register empty interrupt |
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| 359 | wire ms_int; // modem status interrupt |
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| 360 | |
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| 361 | // FIFO signals |
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| 362 | reg tf_push; |
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| 363 | reg rf_pop; |
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| 364 | wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; |
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| 365 | wire rf_error_bit; // an error (parity or framing) is inside the fifo |
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| 366 | wire [`UART_FIFO_COUNTER_W-1:0] rf_count; |
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| 367 | wire [`UART_FIFO_COUNTER_W-1:0] tf_count; |
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| 368 | wire [2:0] tstate; |
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| 369 | wire [3:0] rstate; |
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| 370 | wire [9:0] counter_t; |
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| 371 | |
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| 372 | wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo. |
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| 373 | reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle) |
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| 374 | reg [7:0] block_value; // One character length minus stop bit |
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| 375 | |
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| 376 | // Transmitter Instance |
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| 377 | wire serial_out; |
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| 378 | |
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| 379 | uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask); |
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| 380 | |
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| 381 | // Synchronizing and sampling serial RX input |
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| 382 | uart_sync_flops i_uart_sync_flops |
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| 383 | ( |
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| 384 | .rst_i (wb_rst_i), |
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| 385 | .clk_i (clk), |
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| 386 | .stage1_rst_i (1'b0), |
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| 387 | .stage1_clk_en_i (1'b1), |
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| 388 | .async_dat_i (srx_pad_i), |
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| 389 | .sync_dat_o (srx_pad) |
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| 390 | ); |
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| 391 | defparam i_uart_sync_flops.width = 1; |
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| 392 | defparam i_uart_sync_flops.init_value = 1'b1; |
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| 393 | |
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| 394 | // handle loopback |
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| 395 | wire serial_in = loopback ? serial_out : srx_pad; |
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| 396 | assign stx_pad_o = loopback ? 1'b1 : serial_out; |
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| 397 | |
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| 398 | // Receiver Instance |
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| 399 | uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable, |
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| 400 | counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); |
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| 401 | |
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| 402 | |
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| 403 | // Asynchronous reading here because the outputs are sampled in uart_wb.v file |
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| 404 | always @(dl or dlab or ier or iir or scratch |
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| 405 | or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading |
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| 406 | begin |
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| 407 | case (wb_addr_i) |
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| 408 | `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; |
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| 409 | `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier; |
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| 410 | `UART_REG_II : wb_dat_o = {4'b1100,iir}; |
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| 411 | `UART_REG_LC : wb_dat_o = lcr; |
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| 412 | `UART_REG_LS : wb_dat_o = lsr; |
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| 413 | `UART_REG_MS : wb_dat_o = msr; |
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| 414 | `UART_REG_SR : wb_dat_o = scratch; |
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| 415 | default: wb_dat_o = 8'b0; // ?? |
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| 416 | endcase // case(wb_addr_i) |
---|
| 417 | end // always @ (dl or dlab or ier or iir or scratch... |
---|
| 418 | |
---|
| 419 | |
---|
| 420 | // rf_pop signal handling |
---|
| 421 | always @(posedge clk or posedge wb_rst_i) |
---|
| 422 | begin |
---|
| 423 | if (wb_rst_i) |
---|
| 424 | rf_pop <= #1 0; |
---|
| 425 | else |
---|
| 426 | if (rf_pop) // restore the signal to 0 after one clock cycle |
---|
| 427 | rf_pop <= #1 0; |
---|
| 428 | else |
---|
| 429 | if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab) |
---|
| 430 | rf_pop <= #1 1; // advance read pointer |
---|
| 431 | end |
---|
| 432 | |
---|
| 433 | wire lsr_mask_condition; |
---|
| 434 | wire iir_read; |
---|
| 435 | wire msr_read; |
---|
| 436 | wire fifo_read; |
---|
| 437 | wire fifo_write; |
---|
| 438 | |
---|
| 439 | assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab); |
---|
| 440 | assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab); |
---|
| 441 | assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab); |
---|
| 442 | assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab); |
---|
| 443 | assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab); |
---|
| 444 | |
---|
| 445 | // lsr_mask_d delayed signal handling |
---|
| 446 | always @(posedge clk or posedge wb_rst_i) |
---|
| 447 | begin |
---|
| 448 | if (wb_rst_i) |
---|
| 449 | lsr_mask_d <= #1 0; |
---|
| 450 | else // reset bits in the Line Status Register |
---|
| 451 | lsr_mask_d <= #1 lsr_mask_condition; |
---|
| 452 | end |
---|
| 453 | |
---|
| 454 | // lsr_mask is rise detected |
---|
| 455 | assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; |
---|
| 456 | |
---|
| 457 | // msi_reset signal handling |
---|
| 458 | always @(posedge clk or posedge wb_rst_i) |
---|
| 459 | begin |
---|
| 460 | if (wb_rst_i) |
---|
| 461 | msi_reset <= #1 1; |
---|
| 462 | else |
---|
| 463 | if (msi_reset) |
---|
| 464 | msi_reset <= #1 0; |
---|
| 465 | else |
---|
| 466 | if (msr_read) |
---|
| 467 | msi_reset <= #1 1; // reset bits in Modem Status Register |
---|
| 468 | end |
---|
| 469 | |
---|
| 470 | |
---|
| 471 | // |
---|
| 472 | // WRITES AND RESETS // |
---|
| 473 | // |
---|
| 474 | // Line Control Register |
---|
| 475 | always @(posedge clk or posedge wb_rst_i) |
---|
| 476 | if (wb_rst_i) |
---|
| 477 | lcr <= #1 8'b00000011; // 8n1 setting |
---|
| 478 | else |
---|
| 479 | if (wb_we_i && wb_addr_i==`UART_REG_LC) |
---|
| 480 | lcr <= #1 wb_dat_i; |
---|
| 481 | |
---|
| 482 | // Interrupt Enable Register or UART_DL2 |
---|
| 483 | always @(posedge clk or posedge wb_rst_i) |
---|
| 484 | if (wb_rst_i) |
---|
| 485 | begin |
---|
| 486 | ier <= #1 4'b0000; // no interrupts after reset |
---|
| 487 | dl[`UART_DL2] <= #1 8'b0; |
---|
| 488 | end |
---|
| 489 | else |
---|
| 490 | if (wb_we_i && wb_addr_i==`UART_REG_IE) |
---|
| 491 | if (dlab) |
---|
| 492 | begin |
---|
| 493 | dl[`UART_DL2] <= #1 wb_dat_i; |
---|
| 494 | end |
---|
| 495 | else |
---|
| 496 | ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb |
---|
| 497 | |
---|
| 498 | |
---|
| 499 | // FIFO Control Register and rx_reset, tx_reset signals |
---|
| 500 | always @(posedge clk or posedge wb_rst_i) |
---|
| 501 | if (wb_rst_i) begin |
---|
| 502 | fcr <= #1 2'b11; |
---|
| 503 | rx_reset <= #1 0; |
---|
| 504 | tx_reset <= #1 0; |
---|
| 505 | end else |
---|
| 506 | if (wb_we_i && wb_addr_i==`UART_REG_FC) begin |
---|
| 507 | fcr <= #1 wb_dat_i[7:6]; |
---|
| 508 | rx_reset <= #1 wb_dat_i[1]; |
---|
| 509 | tx_reset <= #1 wb_dat_i[2]; |
---|
| 510 | end else begin |
---|
| 511 | rx_reset <= #1 0; |
---|
| 512 | tx_reset <= #1 0; |
---|
| 513 | end |
---|
| 514 | |
---|
| 515 | // Modem Control Register |
---|
| 516 | always @(posedge clk or posedge wb_rst_i) |
---|
| 517 | if (wb_rst_i) |
---|
| 518 | mcr <= #1 5'b0; |
---|
| 519 | else |
---|
| 520 | if (wb_we_i && wb_addr_i==`UART_REG_MC) |
---|
| 521 | mcr <= #1 wb_dat_i[4:0]; |
---|
| 522 | |
---|
| 523 | // Scratch register |
---|
| 524 | // Line Control Register |
---|
| 525 | always @(posedge clk or posedge wb_rst_i) |
---|
| 526 | if (wb_rst_i) |
---|
| 527 | scratch <= #1 0; // 8n1 setting |
---|
| 528 | else |
---|
| 529 | if (wb_we_i && wb_addr_i==`UART_REG_SR) |
---|
| 530 | scratch <= #1 wb_dat_i; |
---|
| 531 | |
---|
| 532 | // TX_FIFO or UART_DL1 |
---|
| 533 | always @(posedge clk or posedge wb_rst_i) |
---|
| 534 | if (wb_rst_i) |
---|
| 535 | begin |
---|
| 536 | dl[`UART_DL1] <= #1 8'b0; |
---|
| 537 | tf_push <= #1 1'b0; |
---|
| 538 | start_dlc <= #1 1'b0; |
---|
| 539 | end |
---|
| 540 | else |
---|
| 541 | if (wb_we_i && wb_addr_i==`UART_REG_TR) |
---|
| 542 | if (dlab) |
---|
| 543 | begin |
---|
| 544 | dl[`UART_DL1] <= #1 wb_dat_i; |
---|
| 545 | start_dlc <= #1 1'b1; // enable DL counter |
---|
| 546 | tf_push <= #1 1'b0; |
---|
| 547 | end |
---|
| 548 | else |
---|
| 549 | begin |
---|
| 550 | tf_push <= #1 1'b1; |
---|
| 551 | start_dlc <= #1 1'b0; |
---|
| 552 | end // else: !if(dlab) |
---|
| 553 | else |
---|
| 554 | begin |
---|
| 555 | start_dlc <= #1 1'b0; |
---|
| 556 | tf_push <= #1 1'b0; |
---|
| 557 | end // else: !if(dlab) |
---|
| 558 | |
---|
| 559 | // Receiver FIFO trigger level selection logic (asynchronous mux) |
---|
| 560 | always @(fcr) |
---|
| 561 | case (fcr[`UART_FC_TL]) |
---|
| 562 | 2'b00 : trigger_level = 1; |
---|
| 563 | 2'b01 : trigger_level = 4; |
---|
| 564 | 2'b10 : trigger_level = 8; |
---|
| 565 | 2'b11 : trigger_level = 14; |
---|
| 566 | endcase // case(fcr[`UART_FC_TL]) |
---|
| 567 | |
---|
| 568 | // |
---|
| 569 | // STATUS REGISTERS // |
---|
| 570 | // |
---|
| 571 | |
---|
| 572 | // Modem Status Register |
---|
| 573 | reg [3:0] delayed_modem_signals; |
---|
| 574 | always @(posedge clk or posedge wb_rst_i) |
---|
| 575 | begin |
---|
| 576 | if (wb_rst_i) |
---|
| 577 | begin |
---|
| 578 | msr <= #1 0; |
---|
| 579 | delayed_modem_signals[3:0] <= #1 0; |
---|
| 580 | end |
---|
| 581 | else begin |
---|
| 582 | msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 : |
---|
| 583 | msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); |
---|
| 584 | msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c}; |
---|
| 585 | delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts}; |
---|
| 586 | end |
---|
| 587 | end |
---|
| 588 | |
---|
| 589 | |
---|
| 590 | // Line Status Register |
---|
| 591 | |
---|
| 592 | // activation conditions |
---|
| 593 | assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition |
---|
| 594 | assign lsr1 = rf_overrun; // Receiver overrun error |
---|
| 595 | assign lsr2 = rf_data_out[1]; // parity error bit |
---|
| 596 | assign lsr3 = rf_data_out[0]; // framing error bit |
---|
| 597 | assign lsr4 = rf_data_out[2]; // break error in the character |
---|
| 598 | assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty |
---|
| 599 | assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty |
---|
| 600 | assign lsr7 = rf_error_bit | rf_overrun; |
---|
| 601 | |
---|
| 602 | // lsr bit0 (receiver data available) |
---|
| 603 | reg lsr0_d; |
---|
| 604 | |
---|
| 605 | always @(posedge clk or posedge wb_rst_i) |
---|
| 606 | if (wb_rst_i) lsr0_d <= #1 0; |
---|
| 607 | else lsr0_d <= #1 lsr0; |
---|
| 608 | |
---|
| 609 | always @(posedge clk or posedge wb_rst_i) |
---|
| 610 | if (wb_rst_i) lsr0r <= #1 0; |
---|
| 611 | else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition |
---|
| 612 | lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted |
---|
| 613 | |
---|
| 614 | // lsr bit 1 (receiver overrun) |
---|
| 615 | reg lsr1_d; // delayed |
---|
| 616 | |
---|
| 617 | always @(posedge clk or posedge wb_rst_i) |
---|
| 618 | if (wb_rst_i) lsr1_d <= #1 0; |
---|
| 619 | else lsr1_d <= #1 lsr1; |
---|
| 620 | |
---|
| 621 | always @(posedge clk or posedge wb_rst_i) |
---|
| 622 | if (wb_rst_i) lsr1r <= #1 0; |
---|
| 623 | else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise |
---|
| 624 | |
---|
| 625 | // lsr bit 2 (parity error) |
---|
| 626 | reg lsr2_d; // delayed |
---|
| 627 | |
---|
| 628 | always @(posedge clk or posedge wb_rst_i) |
---|
| 629 | if (wb_rst_i) lsr2_d <= #1 0; |
---|
| 630 | else lsr2_d <= #1 lsr2; |
---|
| 631 | |
---|
| 632 | always @(posedge clk or posedge wb_rst_i) |
---|
| 633 | if (wb_rst_i) lsr2r <= #1 0; |
---|
| 634 | else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise |
---|
| 635 | |
---|
| 636 | // lsr bit 3 (framing error) |
---|
| 637 | reg lsr3_d; // delayed |
---|
| 638 | |
---|
| 639 | always @(posedge clk or posedge wb_rst_i) |
---|
| 640 | if (wb_rst_i) lsr3_d <= #1 0; |
---|
| 641 | else lsr3_d <= #1 lsr3; |
---|
| 642 | |
---|
| 643 | always @(posedge clk or posedge wb_rst_i) |
---|
| 644 | if (wb_rst_i) lsr3r <= #1 0; |
---|
| 645 | else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise |
---|
| 646 | |
---|
| 647 | // lsr bit 4 (break indicator) |
---|
| 648 | reg lsr4_d; // delayed |
---|
| 649 | |
---|
| 650 | always @(posedge clk or posedge wb_rst_i) |
---|
| 651 | if (wb_rst_i) lsr4_d <= #1 0; |
---|
| 652 | else lsr4_d <= #1 lsr4; |
---|
| 653 | |
---|
| 654 | always @(posedge clk or posedge wb_rst_i) |
---|
| 655 | if (wb_rst_i) lsr4r <= #1 0; |
---|
| 656 | else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d); |
---|
| 657 | |
---|
| 658 | // lsr bit 5 (transmitter fifo is empty) |
---|
| 659 | reg lsr5_d; |
---|
| 660 | |
---|
| 661 | always @(posedge clk or posedge wb_rst_i) |
---|
| 662 | if (wb_rst_i) lsr5_d <= #1 1; |
---|
| 663 | else lsr5_d <= #1 lsr5; |
---|
| 664 | |
---|
| 665 | always @(posedge clk or posedge wb_rst_i) |
---|
| 666 | if (wb_rst_i) lsr5r <= #1 1; |
---|
| 667 | else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d); |
---|
| 668 | |
---|
| 669 | // lsr bit 6 (transmitter empty indicator) |
---|
| 670 | reg lsr6_d; |
---|
| 671 | |
---|
| 672 | always @(posedge clk or posedge wb_rst_i) |
---|
| 673 | if (wb_rst_i) lsr6_d <= #1 1; |
---|
| 674 | else lsr6_d <= #1 lsr6; |
---|
| 675 | |
---|
| 676 | always @(posedge clk or posedge wb_rst_i) |
---|
| 677 | if (wb_rst_i) lsr6r <= #1 1; |
---|
| 678 | else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d); |
---|
| 679 | |
---|
| 680 | // lsr bit 7 (error in fifo) |
---|
| 681 | reg lsr7_d; |
---|
| 682 | |
---|
| 683 | always @(posedge clk or posedge wb_rst_i) |
---|
| 684 | if (wb_rst_i) lsr7_d <= #1 0; |
---|
| 685 | else lsr7_d <= #1 lsr7; |
---|
| 686 | |
---|
| 687 | always @(posedge clk or posedge wb_rst_i) |
---|
| 688 | if (wb_rst_i) lsr7r <= #1 0; |
---|
| 689 | else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d); |
---|
| 690 | |
---|
| 691 | // Frequency divider |
---|
| 692 | always @(posedge clk or posedge wb_rst_i) |
---|
| 693 | begin |
---|
| 694 | if (wb_rst_i) |
---|
| 695 | dlc <= #1 0; |
---|
| 696 | else |
---|
| 697 | if (start_dlc | ~ (|dlc)) |
---|
| 698 | dlc <= #1 dl - 1; // preset counter |
---|
| 699 | else |
---|
| 700 | dlc <= #1 dlc - 1; // decrement counter |
---|
| 701 | end |
---|
| 702 | |
---|
| 703 | // Enable signal generation logic |
---|
| 704 | always @(posedge clk or posedge wb_rst_i) |
---|
| 705 | begin |
---|
| 706 | if (wb_rst_i) |
---|
| 707 | enable <= #1 1'b0; |
---|
| 708 | else |
---|
| 709 | if (|dl & ~(|dlc)) // dl>0 & dlc==0 |
---|
| 710 | enable <= #1 1'b1; |
---|
| 711 | else |
---|
| 712 | enable <= #1 1'b0; |
---|
| 713 | end |
---|
| 714 | |
---|
| 715 | // Delaying THRE status for one character cycle after a character is written to an empty fifo. |
---|
| 716 | always @(lcr) |
---|
| 717 | case (lcr[3:0]) |
---|
| 718 | 4'b0000 : block_value = 95; // 6 bits |
---|
| 719 | 4'b0100 : block_value = 103; // 6.5 bits |
---|
| 720 | 4'b0001, 4'b1000 : block_value = 111; // 7 bits |
---|
| 721 | 4'b1100 : block_value = 119; // 7.5 bits |
---|
| 722 | 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits |
---|
| 723 | 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits |
---|
| 724 | 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits |
---|
| 725 | 4'b1111 : block_value = 175; // 11 bits |
---|
| 726 | endcase // case(lcr[3:0]) |
---|
| 727 | |
---|
| 728 | // Counting time of one character minus stop bit |
---|
| 729 | always @(posedge clk or posedge wb_rst_i) |
---|
| 730 | begin |
---|
| 731 | if (wb_rst_i) |
---|
| 732 | block_cnt <= #1 8'd0; |
---|
| 733 | else |
---|
| 734 | if(lsr5r & fifo_write) // THRE bit set & write to fifo occured |
---|
| 735 | block_cnt <= #1 block_value; |
---|
| 736 | else |
---|
| 737 | if (enable & block_cnt != 8'b0) // only work on enable times |
---|
| 738 | block_cnt <= #1 block_cnt - 1; // decrement break counter |
---|
| 739 | end // always of break condition detection |
---|
| 740 | |
---|
| 741 | // Generating THRE status enable signal |
---|
| 742 | assign thre_set_en = ~(|block_cnt); |
---|
| 743 | |
---|
| 744 | |
---|
| 745 | // |
---|
| 746 | // INTERRUPT LOGIC |
---|
| 747 | // |
---|
| 748 | |
---|
| 749 | assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); |
---|
| 750 | assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); |
---|
| 751 | assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE]; |
---|
| 752 | assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]); |
---|
| 753 | assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); |
---|
| 754 | |
---|
| 755 | reg rls_int_d; |
---|
| 756 | reg thre_int_d; |
---|
| 757 | reg ms_int_d; |
---|
| 758 | reg ti_int_d; |
---|
| 759 | reg rda_int_d; |
---|
| 760 | |
---|
| 761 | // delay lines |
---|
| 762 | always @(posedge clk or posedge wb_rst_i) |
---|
| 763 | if (wb_rst_i) rls_int_d <= #1 0; |
---|
| 764 | else rls_int_d <= #1 rls_int; |
---|
| 765 | |
---|
| 766 | always @(posedge clk or posedge wb_rst_i) |
---|
| 767 | if (wb_rst_i) rda_int_d <= #1 0; |
---|
| 768 | else rda_int_d <= #1 rda_int; |
---|
| 769 | |
---|
| 770 | always @(posedge clk or posedge wb_rst_i) |
---|
| 771 | if (wb_rst_i) thre_int_d <= #1 0; |
---|
| 772 | else thre_int_d <= #1 thre_int; |
---|
| 773 | |
---|
| 774 | always @(posedge clk or posedge wb_rst_i) |
---|
| 775 | if (wb_rst_i) ms_int_d <= #1 0; |
---|
| 776 | else ms_int_d <= #1 ms_int; |
---|
| 777 | |
---|
| 778 | always @(posedge clk or posedge wb_rst_i) |
---|
| 779 | if (wb_rst_i) ti_int_d <= #1 0; |
---|
| 780 | else ti_int_d <= #1 ti_int; |
---|
| 781 | |
---|
| 782 | // rise detection signals |
---|
| 783 | |
---|
| 784 | wire rls_int_rise; |
---|
| 785 | wire thre_int_rise; |
---|
| 786 | wire ms_int_rise; |
---|
| 787 | wire ti_int_rise; |
---|
| 788 | wire rda_int_rise; |
---|
| 789 | |
---|
| 790 | assign rda_int_rise = rda_int & ~rda_int_d; |
---|
| 791 | assign rls_int_rise = rls_int & ~rls_int_d; |
---|
| 792 | assign thre_int_rise = thre_int & ~thre_int_d; |
---|
| 793 | assign ms_int_rise = ms_int & ~ms_int_d; |
---|
| 794 | assign ti_int_rise = ti_int & ~ti_int_d; |
---|
| 795 | |
---|
| 796 | // interrupt pending flags |
---|
| 797 | reg rls_int_pnd; |
---|
| 798 | reg rda_int_pnd; |
---|
| 799 | reg thre_int_pnd; |
---|
| 800 | reg ms_int_pnd; |
---|
| 801 | reg ti_int_pnd; |
---|
| 802 | |
---|
| 803 | // interrupt pending flags assignments |
---|
| 804 | always @(posedge clk or posedge wb_rst_i) |
---|
| 805 | if (wb_rst_i) rls_int_pnd <= #1 0; |
---|
| 806 | else |
---|
| 807 | rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition |
---|
| 808 | rls_int_rise ? 1 : // latch condition |
---|
| 809 | rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked |
---|
| 810 | |
---|
| 811 | always @(posedge clk or posedge wb_rst_i) |
---|
| 812 | if (wb_rst_i) rda_int_pnd <= #1 0; |
---|
| 813 | else |
---|
| 814 | rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition |
---|
| 815 | rda_int_rise ? 1 : // latch condition |
---|
| 816 | rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked |
---|
| 817 | |
---|
| 818 | always @(posedge clk or posedge wb_rst_i) |
---|
| 819 | if (wb_rst_i) thre_int_pnd <= #1 0; |
---|
| 820 | else |
---|
| 821 | thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 : |
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| 822 | thre_int_rise ? 1 : |
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| 823 | thre_int_pnd && ier[`UART_IE_THRE]; |
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| 824 | |
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| 825 | always @(posedge clk or posedge wb_rst_i) |
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| 826 | if (wb_rst_i) ms_int_pnd <= #1 0; |
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| 827 | else |
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| 828 | ms_int_pnd <= #1 msr_read ? 0 : |
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| 829 | ms_int_rise ? 1 : |
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| 830 | ms_int_pnd && ier[`UART_IE_MS]; |
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| 831 | |
---|
| 832 | always @(posedge clk or posedge wb_rst_i) |
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| 833 | if (wb_rst_i) ti_int_pnd <= #1 0; |
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| 834 | else |
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| 835 | ti_int_pnd <= #1 fifo_read ? 0 : |
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| 836 | ti_int_rise ? 1 : |
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| 837 | ti_int_pnd && ier[`UART_IE_RDA]; |
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| 838 | // end of pending flags |
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| 839 | |
---|
| 840 | // INT_O logic |
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| 841 | always @(posedge clk or posedge wb_rst_i) |
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| 842 | begin |
---|
| 843 | if (wb_rst_i) |
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| 844 | int_o <= #1 1'b0; |
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| 845 | else |
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| 846 | int_o <= #1 |
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| 847 | rls_int_pnd ? ~lsr_mask : |
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| 848 | rda_int_pnd ? 1 : |
---|
| 849 | ti_int_pnd ? ~fifo_read : |
---|
| 850 | thre_int_pnd ? !(fifo_write & iir_read) : |
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| 851 | ms_int_pnd ? ~msr_read : |
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| 852 | 0; // if no interrupt are pending |
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| 853 | end |
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| 854 | |
---|
| 855 | |
---|
| 856 | // Interrupt Identification register |
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| 857 | always @(posedge clk or posedge wb_rst_i) |
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| 858 | begin |
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| 859 | if (wb_rst_i) |
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| 860 | iir <= #1 1; |
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| 861 | else |
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| 862 | if (rls_int_pnd) // interrupt is pending |
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| 863 | begin |
---|
| 864 | iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value |
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| 865 | iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending) |
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| 866 | end else // the sequence of conditions determines priority of interrupt identification |
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| 867 | if (rda_int) |
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| 868 | begin |
---|
| 869 | iir[`UART_II_II] <= #1 `UART_II_RDA; |
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| 870 | iir[`UART_II_IP] <= #1 1'b0; |
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| 871 | end |
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| 872 | else if (ti_int_pnd) |
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| 873 | begin |
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| 874 | iir[`UART_II_II] <= #1 `UART_II_TI; |
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| 875 | iir[`UART_II_IP] <= #1 1'b0; |
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| 876 | end |
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| 877 | else if (thre_int_pnd) |
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| 878 | begin |
---|
| 879 | iir[`UART_II_II] <= #1 `UART_II_THRE; |
---|
| 880 | iir[`UART_II_IP] <= #1 1'b0; |
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| 881 | end |
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| 882 | else if (ms_int_pnd) |
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| 883 | begin |
---|
| 884 | iir[`UART_II_II] <= #1 `UART_II_MS; |
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| 885 | iir[`UART_II_IP] <= #1 1'b0; |
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| 886 | end else // no interrupt is pending |
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| 887 | begin |
---|
| 888 | iir[`UART_II_II] <= #1 0; |
---|
| 889 | iir[`UART_II_IP] <= #1 1'b1; |
---|
| 890 | end |
---|
| 891 | end |
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| 892 | |
---|
| 893 | endmodule |
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