| 1 | ////////////////////////////////////////////////////////////////////// |
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| 2 | //// //// |
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| 3 | //// uart_receiver.v //// |
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| 4 | //// //// |
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| 5 | //// //// |
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| 6 | //// This file is part of the "UART 16550 compatible" project //// |
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| 7 | //// http://www.opencores.org/cores/uart16550/ //// |
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| 8 | //// //// |
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| 9 | //// Documentation related to this project: //// |
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| 10 | //// - http://www.opencores.org/cores/uart16550/ //// |
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| 11 | //// //// |
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| 12 | //// Projects compatibility: //// |
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| 13 | //// - WISHBONE //// |
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| 14 | //// RS232 Protocol //// |
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| 15 | //// 16550D uart (mostly supported) //// |
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| 16 | //// //// |
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| 17 | //// Overview (main Features): //// |
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| 18 | //// UART core receiver logic //// |
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| 19 | //// //// |
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| 20 | //// Known problems (limits): //// |
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| 21 | //// None known //// |
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| 22 | //// //// |
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| 23 | //// To Do: //// |
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| 24 | //// Thourough testing. //// |
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| 25 | //// //// |
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| 26 | //// Author(s): //// |
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| 27 | //// - [email protected] //// |
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| 28 | //// - Jacob Gorban //// |
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| 29 | //// - Igor Mohor ([email protected]) //// |
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| 30 | //// //// |
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| 31 | //// Created: 2001/05/12 //// |
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| 32 | //// Last Updated: 2001/05/17 //// |
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| 33 | //// (See log for the revision history) //// |
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| 34 | //// //// |
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| 35 | //// //// |
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| 36 | ////////////////////////////////////////////////////////////////////// |
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| 37 | //// //// |
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| 38 | //// Copyright (C) 2000, 2001 Authors //// |
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| 39 | //// //// |
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| 40 | //// This source file may be used and distributed without //// |
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| 41 | //// restriction provided that this copyright statement is not //// |
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| 42 | //// removed from the file and that any derivative work contains //// |
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| 43 | //// the original copyright notice and the associated disclaimer. //// |
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| 44 | //// //// |
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| 45 | //// This source file is free software; you can redistribute it //// |
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| 46 | //// and/or modify it under the terms of the GNU Lesser General //// |
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| 47 | //// Public License as published by the Free Software Foundation; //// |
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| 48 | //// either version 2.1 of the License, or (at your option) any //// |
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| 49 | //// later version. //// |
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| 50 | //// //// |
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| 51 | //// This source is distributed in the hope that it will be //// |
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| 52 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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| 53 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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| 54 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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| 55 | //// details. //// |
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| 56 | //// //// |
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| 57 | //// You should have received a copy of the GNU Lesser General //// |
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| 58 | //// Public License along with this source; if not, download it //// |
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| 59 | //// from http://www.opencores.org/lgpl.shtml //// |
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| 60 | //// //// |
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| 61 | ////////////////////////////////////////////////////////////////////// |
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| 62 | // |
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| 63 | // CVS Revision History |
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| 64 | // |
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| 65 | // $Log: not supported by cvs2svn $ |
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| 66 | // Revision 1.29 2002/07/29 21:16:18 gorban |
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| 67 | // The uart_defines.v file is included again in sources. |
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| 68 | // |
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| 69 | // Revision 1.28 2002/07/22 23:02:23 gorban |
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| 70 | // Bug Fixes: |
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| 71 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
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| 72 | // Problem reported by Kenny.Tung. |
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| 73 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
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| 74 | // |
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| 75 | // Improvements: |
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| 76 | // * Made FIFO's as general inferrable memory where possible. |
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| 77 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
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| 78 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
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| 79 | // |
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| 80 | // * Added optional baudrate output (baud_o). |
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| 81 | // This is identical to BAUDOUT* signal on 16550 chip. |
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| 82 | // It outputs 16xbit_clock_rate - the divided clock. |
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| 83 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
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| 84 | // |
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| 85 | // Revision 1.27 2001/12/30 20:39:13 mohor |
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| 86 | // More than one character was stored in case of break. End of the break |
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| 87 | // was not detected correctly. |
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| 88 | // |
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| 89 | // Revision 1.26 2001/12/20 13:28:27 mohor |
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| 90 | // Missing declaration of rf_push_q fixed. |
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| 91 | // |
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| 92 | // Revision 1.25 2001/12/20 13:25:46 mohor |
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| 93 | // rx push changed to be only one cycle wide. |
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| 94 | // |
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| 95 | // Revision 1.24 2001/12/19 08:03:34 mohor |
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| 96 | // Warnings cleared. |
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| 97 | // |
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| 98 | // Revision 1.23 2001/12/19 07:33:54 mohor |
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| 99 | // Synplicity was having troubles with the comment. |
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| 100 | // |
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| 101 | // Revision 1.22 2001/12/17 14:46:48 mohor |
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| 102 | // overrun signal was moved to separate block because many sequential lsr |
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| 103 | // reads were preventing data from being written to rx fifo. |
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| 104 | // underrun signal was not used and was removed from the project. |
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| 105 | // |
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| 106 | // Revision 1.21 2001/12/13 10:31:16 mohor |
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| 107 | // timeout irq must be set regardless of the rda irq (rda irq does not reset the |
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| 108 | // timeout counter). |
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| 109 | // |
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| 110 | // Revision 1.20 2001/12/10 19:52:05 gorban |
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| 111 | // Igor fixed break condition bugs |
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| 112 | // |
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| 113 | // Revision 1.19 2001/12/06 14:51:04 gorban |
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| 114 | // Bug in LSR[0] is fixed. |
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| 115 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. |
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| 116 | // |
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| 117 | // Revision 1.18 2001/12/03 21:44:29 gorban |
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| 118 | // Updated specification documentation. |
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| 119 | // Added full 32-bit data bus interface, now as default. |
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| 120 | // Address is 5-bit wide in 32-bit data bus mode. |
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| 121 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. |
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| 122 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. |
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| 123 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. |
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| 124 | // My small test bench is modified to work with 32-bit mode. |
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| 125 | // |
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| 126 | // Revision 1.17 2001/11/28 19:36:39 gorban |
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| 127 | // Fixed: timeout and break didn't pay attention to current data format when counting time |
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| 128 | // |
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| 129 | // Revision 1.16 2001/11/27 22:17:09 gorban |
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| 130 | // Fixed bug that prevented synthesis in uart_receiver.v |
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| 131 | // |
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| 132 | // Revision 1.15 2001/11/26 21:38:54 gorban |
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| 133 | // Lots of fixes: |
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| 134 | // Break condition wasn't handled correctly at all. |
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| 135 | // LSR bits could lose their values. |
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| 136 | // LSR value after reset was wrong. |
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| 137 | // Timing of THRE interrupt signal corrected. |
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| 138 | // LSR bit 0 timing corrected. |
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| 139 | // |
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| 140 | // Revision 1.14 2001/11/10 12:43:21 gorban |
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| 141 | // Logic Synthesis bugs fixed. Some other minor changes |
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| 142 | // |
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| 143 | // Revision 1.13 2001/11/08 14:54:23 mohor |
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| 144 | // Comments in Slovene language deleted, few small fixes for better work of |
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| 145 | // old tools. IRQs need to be fix. |
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| 146 | // |
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| 147 | // Revision 1.12 2001/11/07 17:51:52 gorban |
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| 148 | // Heavily rewritten interrupt and LSR subsystems. |
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| 149 | // Many bugs hopefully squashed. |
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| 150 | // |
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| 151 | // Revision 1.11 2001/10/31 15:19:22 gorban |
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| 152 | // Fixes to break and timeout conditions |
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| 153 | // |
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| 154 | // Revision 1.10 2001/10/20 09:58:40 gorban |
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| 155 | // Small synopsis fixes |
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| 156 | // |
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| 157 | // Revision 1.9 2001/08/24 21:01:12 mohor |
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| 158 | // Things connected to parity changed. |
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| 159 | // Clock devider changed. |
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| 160 | // |
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| 161 | // Revision 1.8 2001/08/23 16:05:05 mohor |
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| 162 | // Stop bit bug fixed. |
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| 163 | // Parity bug fixed. |
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| 164 | // WISHBONE read cycle bug fixed, |
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| 165 | // OE indicator (Overrun Error) bug fixed. |
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| 166 | // PE indicator (Parity Error) bug fixed. |
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| 167 | // Register read bug fixed. |
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| 168 | // |
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| 169 | // Revision 1.6 2001/06/23 11:21:48 gorban |
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| 170 | // DL made 16-bit long. Fixed transmission/reception bugs. |
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| 171 | // |
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| 172 | // Revision 1.5 2001/06/02 14:28:14 gorban |
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| 173 | // Fixed receiver and transmitter. Major bug fixed. |
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| 174 | // |
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| 175 | // Revision 1.4 2001/05/31 20:08:01 gorban |
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| 176 | // FIFO changes and other corrections. |
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| 177 | // |
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| 178 | // Revision 1.3 2001/05/27 17:37:49 gorban |
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| 179 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. |
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| 180 | // |
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| 181 | // Revision 1.2 2001/05/21 19:12:02 gorban |
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| 182 | // Corrected some Linter messages. |
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| 183 | // |
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| 184 | // Revision 1.1 2001/05/17 18:34:18 gorban |
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| 185 | // First 'stable' release. Should be sythesizable now. Also added new header. |
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| 186 | // |
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| 187 | // Revision 1.0 2001-05-17 21:27:11+02 jacob |
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| 188 | // Initial revision |
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| 189 | // |
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| 190 | // |
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| 191 | |
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| 192 | // synopsys translate_off |
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| 193 | `include "timescale.v" |
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| 194 | // synopsys translate_on |
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| 195 | |
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| 196 | `include "uart_defines.v" |
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| 197 | |
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| 198 | module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, |
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| 199 | counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); |
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| 200 | |
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| 201 | input clk; |
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| 202 | input wb_rst_i; |
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| 203 | input [7:0] lcr; |
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| 204 | input rf_pop; |
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| 205 | input srx_pad_i; |
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| 206 | input enable; |
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| 207 | input rx_reset; |
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| 208 | input lsr_mask; |
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| 209 | |
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| 210 | output [9:0] counter_t; |
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| 211 | output [`UART_FIFO_COUNTER_W-1:0] rf_count; |
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| 212 | output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; |
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| 213 | output rf_overrun; |
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| 214 | output rf_error_bit; |
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| 215 | output [3:0] rstate; |
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| 216 | output rf_push_pulse; |
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| 217 | |
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| 218 | reg [3:0] rstate; |
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| 219 | reg [3:0] rcounter16; |
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| 220 | reg [2:0] rbit_counter; |
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| 221 | reg [7:0] rshift; // receiver shift register |
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| 222 | reg rparity; // received parity |
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| 223 | reg rparity_error; |
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| 224 | reg rframing_error; // framing error flag |
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| 225 | reg rbit_in; |
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| 226 | reg rparity_xor; |
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| 227 | reg [7:0] counter_b; // counts the 0 (low) signals |
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| 228 | reg rf_push_q; |
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| 229 | |
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| 230 | // RX FIFO signals |
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| 231 | reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; |
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| 232 | wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; |
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| 233 | wire rf_push_pulse; |
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| 234 | reg rf_push; |
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| 235 | wire rf_pop; |
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| 236 | wire rf_overrun; |
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| 237 | wire [`UART_FIFO_COUNTER_W-1:0] rf_count; |
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| 238 | wire rf_error_bit; // an error (parity or framing) is inside the fifo |
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| 239 | wire break_error = (counter_b == 0); |
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| 240 | |
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| 241 | // RX FIFO instance |
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| 242 | uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( |
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| 243 | .clk( clk ), |
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| 244 | .wb_rst_i( wb_rst_i ), |
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| 245 | .data_in( rf_data_in ), |
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| 246 | .data_out( rf_data_out ), |
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| 247 | .push( rf_push_pulse ), |
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| 248 | .pop( rf_pop ), |
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| 249 | .overrun( rf_overrun ), |
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| 250 | .count( rf_count ), |
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| 251 | .error_bit( rf_error_bit ), |
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| 252 | .fifo_reset( rx_reset ), |
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| 253 | .reset_status(lsr_mask) |
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| 254 | ); |
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| 255 | |
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| 256 | wire rcounter16_eq_7 = (rcounter16 == 4'd7); |
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| 257 | wire rcounter16_eq_0 = (rcounter16 == 4'd0); |
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| 258 | wire rcounter16_eq_1 = (rcounter16 == 4'd1); |
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| 259 | |
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| 260 | wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1; |
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| 261 | |
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| 262 | parameter sr_idle = 4'd0; |
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| 263 | parameter sr_rec_start = 4'd1; |
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| 264 | parameter sr_rec_bit = 4'd2; |
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| 265 | parameter sr_rec_parity = 4'd3; |
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| 266 | parameter sr_rec_stop = 4'd4; |
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| 267 | parameter sr_check_parity = 4'd5; |
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| 268 | parameter sr_rec_prepare = 4'd6; |
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| 269 | parameter sr_end_bit = 4'd7; |
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| 270 | parameter sr_ca_lc_parity = 4'd8; |
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| 271 | parameter sr_wait1 = 4'd9; |
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| 272 | parameter sr_push = 4'd10; |
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| 273 | |
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| 274 | |
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| 275 | always @(posedge clk or posedge wb_rst_i) |
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| 276 | begin |
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| 277 | if (wb_rst_i) |
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| 278 | begin |
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| 279 | rstate <= #1 sr_idle; |
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| 280 | rbit_in <= #1 1'b0; |
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| 281 | rcounter16 <= #1 0; |
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| 282 | rbit_counter <= #1 0; |
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| 283 | rparity_xor <= #1 1'b0; |
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| 284 | rframing_error <= #1 1'b0; |
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| 285 | rparity_error <= #1 1'b0; |
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| 286 | rparity <= #1 1'b0; |
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| 287 | rshift <= #1 0; |
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| 288 | rf_push <= #1 1'b0; |
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| 289 | rf_data_in <= #1 0; |
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| 290 | end |
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| 291 | else |
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| 292 | if (enable) |
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| 293 | begin |
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| 294 | case (rstate) |
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| 295 | sr_idle : begin |
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| 296 | rf_push <= #1 1'b0; |
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| 297 | rf_data_in <= #1 0; |
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| 298 | rcounter16 <= #1 4'b1110; |
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| 299 | if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?) |
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| 300 | begin |
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| 301 | rstate <= #1 sr_rec_start; |
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| 302 | end |
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| 303 | end |
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| 304 | sr_rec_start : begin |
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| 305 | rf_push <= #1 1'b0; |
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| 306 | if (rcounter16_eq_7) // check the pulse |
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| 307 | if (srx_pad_i==1'b1) // no start bit |
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| 308 | rstate <= #1 sr_idle; |
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| 309 | else // start bit detected |
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| 310 | rstate <= #1 sr_rec_prepare; |
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| 311 | rcounter16 <= #1 rcounter16_minus_1; |
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| 312 | end |
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| 313 | sr_rec_prepare:begin |
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| 314 | case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
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| 315 | 2'b00 : rbit_counter <= #1 3'b100; |
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| 316 | 2'b01 : rbit_counter <= #1 3'b101; |
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| 317 | 2'b10 : rbit_counter <= #1 3'b110; |
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| 318 | 2'b11 : rbit_counter <= #1 3'b111; |
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| 319 | endcase |
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| 320 | if (rcounter16_eq_0) |
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| 321 | begin |
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| 322 | rstate <= #1 sr_rec_bit; |
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| 323 | rcounter16 <= #1 4'b1110; |
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| 324 | rshift <= #1 0; |
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| 325 | end |
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| 326 | else |
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| 327 | rstate <= #1 sr_rec_prepare; |
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| 328 | rcounter16 <= #1 rcounter16_minus_1; |
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| 329 | end |
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| 330 | sr_rec_bit : begin |
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| 331 | if (rcounter16_eq_0) |
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| 332 | rstate <= #1 sr_end_bit; |
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| 333 | if (rcounter16_eq_7) // read the bit |
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| 334 | case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
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| 335 | 2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]}; |
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| 336 | 2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]}; |
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| 337 | 2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]}; |
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| 338 | 2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]}; |
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| 339 | endcase |
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| 340 | rcounter16 <= #1 rcounter16_minus_1; |
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| 341 | end |
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| 342 | sr_end_bit : begin |
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| 343 | if (rbit_counter==3'b0) // no more bits in word |
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| 344 | if (lcr[`UART_LC_PE]) // choose state based on parity |
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| 345 | rstate <= #1 sr_rec_parity; |
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| 346 | else |
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| 347 | begin |
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| 348 | rstate <= #1 sr_rec_stop; |
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| 349 | rparity_error <= #1 1'b0; // no parity - no error :) |
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| 350 | end |
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| 351 | else // else we have more bits to read |
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| 352 | begin |
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| 353 | rstate <= #1 sr_rec_bit; |
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| 354 | rbit_counter <= #1 rbit_counter - 1'b1; |
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| 355 | end |
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| 356 | rcounter16 <= #1 4'b1110; |
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| 357 | end |
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| 358 | sr_rec_parity: begin |
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| 359 | if (rcounter16_eq_7) // read the parity |
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| 360 | begin |
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| 361 | rparity <= #1 srx_pad_i; |
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| 362 | rstate <= #1 sr_ca_lc_parity; |
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| 363 | end |
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| 364 | rcounter16 <= #1 rcounter16_minus_1; |
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| 365 | end |
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| 366 | sr_ca_lc_parity : begin // rcounter equals 6 |
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| 367 | rcounter16 <= #1 rcounter16_minus_1; |
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| 368 | rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data |
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| 369 | rstate <= #1 sr_check_parity; |
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| 370 | end |
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| 371 | sr_check_parity: begin // rcounter equals 5 |
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| 372 | case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) |
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| 373 | 2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1 |
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| 374 | 2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1 |
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| 375 | 2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd |
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| 376 | 2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0 |
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| 377 | endcase |
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| 378 | rcounter16 <= #1 rcounter16_minus_1; |
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| 379 | rstate <= #1 sr_wait1; |
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| 380 | end |
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| 381 | sr_wait1 : if (rcounter16_eq_0) |
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| 382 | begin |
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| 383 | rstate <= #1 sr_rec_stop; |
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| 384 | rcounter16 <= #1 4'b1110; |
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| 385 | end |
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| 386 | else |
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| 387 | rcounter16 <= #1 rcounter16_minus_1; |
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| 388 | sr_rec_stop : begin |
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| 389 | if (rcounter16_eq_7) // read the parity |
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| 390 | begin |
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| 391 | rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit) |
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| 392 | rstate <= #1 sr_push; |
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| 393 | end |
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| 394 | rcounter16 <= #1 rcounter16_minus_1; |
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| 395 | end |
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| 396 | sr_push : begin |
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| 397 | /////////////////////////////////////// |
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| 398 | // $display($time, ": received: %b", rf_data_in); |
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| 399 | if(srx_pad_i | break_error) |
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| 400 | begin |
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| 401 | if(break_error) |
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| 402 | rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO |
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| 403 | else |
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| 404 | rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; |
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| 405 | rf_push <= #1 1'b1; |
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| 406 | rstate <= #1 sr_idle; |
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| 407 | end |
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| 408 | else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i |
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| 409 | begin |
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| 410 | rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; |
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| 411 | rf_push <= #1 1'b1; |
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| 412 | rcounter16 <= #1 4'b1110; |
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| 413 | rstate <= #1 sr_rec_start; |
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| 414 | end |
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| 415 | |
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| 416 | end |
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| 417 | default : rstate <= #1 sr_idle; |
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| 418 | endcase |
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| 419 | end // if (enable) |
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| 420 | end // always of receiver |
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| 421 | |
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| 422 | always @ (posedge clk or posedge wb_rst_i) |
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| 423 | begin |
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| 424 | if(wb_rst_i) |
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| 425 | rf_push_q <= 0; |
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| 426 | else |
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| 427 | rf_push_q <= #1 rf_push; |
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| 428 | end |
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| 429 | |
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| 430 | assign rf_push_pulse = rf_push & ~rf_push_q; |
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| 431 | |
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| 432 | |
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| 433 | // |
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| 434 | // Break condition detection. |
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| 435 | // Works in conjuction with the receiver state machine |
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| 436 | |
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| 437 | reg [9:0] toc_value; // value to be set to timeout counter |
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| 438 | |
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| 439 | always @(lcr) |
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| 440 | case (lcr[3:0]) |
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| 441 | 4'b0000 : toc_value = 447; // 7 bits |
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| 442 | 4'b0100 : toc_value = 479; // 7.5 bits |
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| 443 | 4'b0001, 4'b1000 : toc_value = 511; // 8 bits |
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| 444 | 4'b1100 : toc_value = 543; // 8.5 bits |
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| 445 | 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits |
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| 446 | 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits |
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| 447 | 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits |
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| 448 | 4'b1111 : toc_value = 767; // 12 bits |
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| 449 | endcase // case(lcr[3:0]) |
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| 450 | |
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| 451 | wire [7:0] brc_value; // value to be set to break counter |
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| 452 | assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times |
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| 453 | |
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| 454 | always @(posedge clk or posedge wb_rst_i) |
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| 455 | begin |
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| 456 | if (wb_rst_i) |
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| 457 | counter_b <= #1 8'd159; |
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| 458 | else |
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| 459 | if (srx_pad_i) |
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| 460 | counter_b <= #1 brc_value; // character time length - 1 |
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| 461 | else |
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| 462 | if(enable & counter_b != 8'b0) // only work on enable times break not reached. |
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| 463 | counter_b <= #1 counter_b - 1; // decrement break counter |
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| 464 | end // always of break condition detection |
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| 465 | |
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| 466 | /// |
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| 467 | /// Timeout condition detection |
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| 468 | reg [9:0] counter_t; // counts the timeout condition clocks |
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| 469 | |
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| 470 | always @(posedge clk or posedge wb_rst_i) |
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| 471 | begin |
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| 472 | if (wb_rst_i) |
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| 473 | counter_t <= #1 10'd639; // 10 bits for the default 8N1 |
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| 474 | else |
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| 475 | if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level |
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| 476 | counter_t <= #1 toc_value; |
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| 477 | else |
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| 478 | if (enable && counter_t != 10'b0) // we don't want to underflow |
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| 479 | counter_t <= #1 counter_t - 1; |
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| 480 | end |
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| 481 | |
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| 482 | endmodule |
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