| [6] | 1 | ////////////////////////////////////////////////////////////////////// |
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| 2 | //// //// |
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| 3 | //// uart_debug_if.v //// |
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| 4 | //// //// |
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| 5 | //// //// |
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| 6 | //// This file is part of the "UART 16550 compatible" project //// |
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| 7 | //// http://www.opencores.org/cores/uart16550/ //// |
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| 8 | //// //// |
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| 9 | //// Documentation related to this project: //// |
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| 10 | //// - http://www.opencores.org/cores/uart16550/ //// |
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| 11 | //// //// |
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| 12 | //// Projects compatibility: //// |
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| 13 | //// - WISHBONE //// |
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| 14 | //// RS232 Protocol //// |
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| 15 | //// 16550D uart (mostly supported) //// |
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| 16 | //// //// |
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| 17 | //// Overview (main Features): //// |
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| 18 | //// UART core debug interface. //// |
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| 19 | //// //// |
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| 20 | //// Author(s): //// |
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| 21 | //// - [email protected] //// |
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| 22 | //// - Jacob Gorban //// |
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| 23 | //// //// |
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| 24 | //// Created: 2001/12/02 //// |
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| 25 | //// (See log for the revision history) //// |
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| 26 | //// //// |
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| 27 | ////////////////////////////////////////////////////////////////////// |
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| 28 | //// //// |
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| 29 | //// Copyright (C) 2000, 2001 Authors //// |
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| 30 | //// //// |
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| 31 | //// This source file may be used and distributed without //// |
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| 32 | //// restriction provided that this copyright statement is not //// |
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| 33 | //// removed from the file and that any derivative work contains //// |
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| 34 | //// the original copyright notice and the associated disclaimer. //// |
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| 35 | //// //// |
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| 36 | //// This source file is free software; you can redistribute it //// |
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| 37 | //// and/or modify it under the terms of the GNU Lesser General //// |
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| 38 | //// Public License as published by the Free Software Foundation; //// |
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| 39 | //// either version 2.1 of the License, or (at your option) any //// |
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| 40 | //// later version. //// |
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| 41 | //// //// |
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| 42 | //// This source is distributed in the hope that it will be //// |
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| 43 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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| 44 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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| 45 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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| 46 | //// details. //// |
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| 47 | //// //// |
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| 48 | //// You should have received a copy of the GNU Lesser General //// |
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| 49 | //// Public License along with this source; if not, download it //// |
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| 50 | //// from http://www.opencores.org/lgpl.shtml //// |
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| 51 | //// //// |
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| 52 | ////////////////////////////////////////////////////////////////////// |
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| 53 | // |
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| 54 | // CVS Revision History |
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| 55 | // |
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| 56 | // $Log: not supported by cvs2svn $ |
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| 57 | // Revision 1.4 2002/07/22 23:02:23 gorban |
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| 58 | // Bug Fixes: |
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| 59 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
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| 60 | // Problem reported by Kenny.Tung. |
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| 61 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
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| 62 | // |
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| 63 | // Improvements: |
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| 64 | // * Made FIFO's as general inferrable memory where possible. |
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| 65 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
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| 66 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
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| 67 | // |
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| 68 | // * Added optional baudrate output (baud_o). |
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| 69 | // This is identical to BAUDOUT* signal on 16550 chip. |
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| 70 | // It outputs 16xbit_clock_rate - the divided clock. |
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| 71 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
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| 72 | // |
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| 73 | // Revision 1.3 2001/12/19 08:40:03 mohor |
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| 74 | // Warnings fixed (unused signals removed). |
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| 75 | // |
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| 76 | // Revision 1.2 2001/12/12 22:17:30 gorban |
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| 77 | // some synthesis bugs fixed |
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| 78 | // |
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| 79 | // Revision 1.1 2001/12/04 21:14:16 gorban |
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| 80 | // committed the debug interface file |
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| 81 | // |
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| 82 | |
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| 83 | // synopsys translate_off |
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| 84 | `include "timescale.v" |
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| 85 | // synopsys translate_on |
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| 86 | |
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| 87 | `include "uart_defines.v" |
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| 88 | |
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| 89 | module uart_debug_if (/*AUTOARG*/ |
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| 90 | // Outputs |
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| 91 | wb_dat32_o, |
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| 92 | // Inputs |
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| 93 | wb_adr_i, ier, iir, fcr, mcr, lcr, msr, |
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| 94 | lsr, rf_count, tf_count, tstate, rstate |
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| 95 | ) ; |
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| 96 | |
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| 97 | input [`UART_ADDR_WIDTH-1:0] wb_adr_i; |
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| 98 | output [31:0] wb_dat32_o; |
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| 99 | input [3:0] ier; |
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| 100 | input [3:0] iir; |
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| 101 | input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored |
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| 102 | input [4:0] mcr; |
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| 103 | input [7:0] lcr; |
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| 104 | input [7:0] msr; |
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| 105 | input [7:0] lsr; |
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| 106 | input [`UART_FIFO_COUNTER_W-1:0] rf_count; |
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| 107 | input [`UART_FIFO_COUNTER_W-1:0] tf_count; |
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| 108 | input [2:0] tstate; |
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| 109 | input [3:0] rstate; |
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| 110 | |
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| 111 | |
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| 112 | wire [`UART_ADDR_WIDTH-1:0] wb_adr_i; |
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| 113 | reg [31:0] wb_dat32_o; |
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| 114 | |
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| 115 | always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr |
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| 116 | or rf_count or rstate or tf_count or tstate or wb_adr_i) |
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| 117 | case (wb_adr_i) |
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| 118 | // 8 + 8 + 4 + 4 + 8 |
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| 119 | 5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr}; |
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| 120 | // 5 + 2 + 5 + 4 + 5 + 3 |
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| 121 | 5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate}; |
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| 122 | default: wb_dat32_o = 0; |
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| 123 | endcase // case(wb_adr_i) |
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| 124 | |
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| 125 | endmodule // uart_debug_if |
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| 126 | |
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