1 | ////////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// eth_shiftreg.v //// |
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4 | //// //// |
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5 | //// This file is part of the Ethernet IP core project //// |
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6 | //// http://www.opencores.org/projects/ethmac/ //// |
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7 | //// //// |
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8 | //// Author(s): //// |
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9 | //// - Igor Mohor ([email protected]) //// |
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10 | //// //// |
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11 | //// All additional information is avaliable in the Readme.txt //// |
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12 | //// file. //// |
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13 | //// //// |
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14 | ////////////////////////////////////////////////////////////////////// |
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15 | //// //// |
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16 | //// Copyright (C) 2001 Authors //// |
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17 | //// //// |
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18 | //// This source file may be used and distributed without //// |
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19 | //// restriction provided that this copyright statement is not //// |
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20 | //// removed from the file and that any derivative work contains //// |
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21 | //// the original copyright notice and the associated disclaimer. //// |
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22 | //// //// |
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23 | //// This source file is free software; you can redistribute it //// |
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24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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25 | //// Public License as published by the Free Software Foundation; //// |
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26 | //// either version 2.1 of the License, or (at your option) any //// |
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27 | //// later version. //// |
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28 | //// //// |
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29 | //// This source is distributed in the hope that it will be //// |
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30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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33 | //// details. //// |
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34 | //// //// |
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35 | //// You should have received a copy of the GNU Lesser General //// |
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36 | //// Public License along with this source; if not, download it //// |
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37 | //// from http://www.opencores.org/lgpl.shtml //// |
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38 | //// //// |
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39 | ////////////////////////////////////////////////////////////////////// |
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40 | // |
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41 | // CVS Revision History |
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42 | // |
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43 | // $Log: not supported by cvs2svn $ |
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44 | // Revision 1.5 2002/08/14 18:16:59 mohor |
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45 | // LinkFail signal was not latching appropriate bit. |
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46 | // |
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47 | // Revision 1.4 2002/03/02 21:06:01 mohor |
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48 | // LinkFail signal was not latching appropriate bit. |
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49 | // |
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50 | // Revision 1.3 2002/01/23 10:28:16 mohor |
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51 | // Link in the header changed. |
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52 | // |
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53 | // Revision 1.2 2001/10/19 08:43:51 mohor |
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54 | // eth_timescale.v changed to timescale.v This is done because of the |
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55 | // simulation of the few cores in a one joined project. |
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56 | // |
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57 | // Revision 1.1 2001/08/06 14:44:29 mohor |
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58 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
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59 | // Include files fixed to contain no path. |
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60 | // File names and module names changed ta have a eth_ prologue in the name. |
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61 | // File eth_timescale.v is used to define timescale |
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62 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. |
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63 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
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64 | // and Mdo_OE. The bidirectional signal must be created on the top level. This |
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65 | // is done due to the ASIC tools. |
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66 | // |
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67 | // Revision 1.1 2001/07/30 21:23:42 mohor |
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68 | // Directory structure changed. Files checked and joind together. |
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69 | // |
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70 | // Revision 1.3 2001/06/01 22:28:56 mohor |
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71 | // This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. |
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72 | // |
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73 | // |
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74 | |
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75 | `include "timescale.v" |
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76 | |
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77 | |
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78 | module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, |
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79 | LatchByte, ShiftedBit, Prsd, LinkFail); |
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80 | |
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81 | |
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82 | parameter Tp=1; |
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83 | |
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84 | input Clk; // Input clock (Host clock) |
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85 | input Reset; // Reset signal |
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86 | input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. |
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87 | input Mdi; // MII input data |
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88 | input [4:0] Fiad; // PHY address |
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89 | input [4:0] Rgad; // Register address (within the selected PHY) |
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90 | input [15:0]CtrlData; // Control data (data to be written to the PHY) |
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91 | input WriteOp; // The current operation is a PHY register write operation |
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92 | input [3:0] ByteSelect; // Byte select |
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93 | input [1:0] LatchByte; // Byte select for latching (read operation) |
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94 | |
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95 | output ShiftedBit; // Bit shifted out of the shift register |
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96 | output[15:0]Prsd; // Read Status Data (data read from the PHY) |
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97 | output LinkFail; // Link Integrity Signal |
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98 | |
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99 | reg [7:0] ShiftReg; // Shift register for shifting the data in and out |
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100 | reg [15:0]Prsd; |
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101 | reg LinkFail; |
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102 | |
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103 | |
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104 | |
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105 | |
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106 | // ShiftReg[7:0] :: Shift Register Data |
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107 | always @ (posedge Clk or posedge Reset) |
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108 | begin |
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109 | if(Reset) |
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110 | begin |
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111 | ShiftReg[7:0] <= #Tp 8'h0; |
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112 | Prsd[15:0] <= #Tp 16'h0; |
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113 | LinkFail <= #Tp 1'b0; |
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114 | end |
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115 | else |
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116 | begin |
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117 | if(MdcEn_n) |
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118 | begin |
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119 | if(|ByteSelect) |
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120 | begin |
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121 | case (ByteSelect[3:0]) // synopsys parallel_case full_case |
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122 | 4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; |
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123 | 4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10}; |
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124 | 4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8]; |
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125 | 4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0]; |
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126 | endcase |
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127 | end |
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128 | else |
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129 | begin |
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130 | ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi}; |
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131 | if(LatchByte[0]) |
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132 | begin |
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133 | Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi}; |
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134 | if(Rgad == 5'h01) |
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135 | LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet |
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136 | end |
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137 | else |
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138 | begin |
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139 | if(LatchByte[1]) |
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140 | Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi}; |
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141 | end |
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142 | end |
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143 | end |
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144 | end |
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145 | end |
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146 | |
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147 | |
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148 | assign ShiftedBit = ShiftReg[7]; |
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149 | |
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150 | |
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151 | endmodule |
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