source: XOpenSparcT1/trunk/OC-Ethernet/eth_shiftreg.v @ 6

Revision 6, 6.5 KB checked in by pntsvt00, 14 years ago (diff)

versione iniziale opensparc

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1//////////////////////////////////////////////////////////////////////
2////                                                              ////
3////  eth_shiftreg.v                                              ////
4////                                                              ////
5////  This file is part of the Ethernet IP core project           ////
6////  http://www.opencores.org/projects/ethmac/                   ////
7////                                                              ////
8////  Author(s):                                                  ////
9////      - Igor Mohor ([email protected])                      ////
10////                                                              ////
11////  All additional information is avaliable in the Readme.txt   ////
12////  file.                                                       ////
13////                                                              ////
14//////////////////////////////////////////////////////////////////////
15////                                                              ////
16//// Copyright (C) 2001 Authors                                   ////
17////                                                              ////
18//// This source file may be used and distributed without         ////
19//// restriction provided that this copyright statement is not    ////
20//// removed from the file and that any derivative work contains  ////
21//// the original copyright notice and the associated disclaimer. ////
22////                                                              ////
23//// This source file is free software; you can redistribute it   ////
24//// and/or modify it under the terms of the GNU Lesser General   ////
25//// Public License as published by the Free Software Foundation; ////
26//// either version 2.1 of the License, or (at your option) any   ////
27//// later version.                                               ////
28////                                                              ////
29//// This source is distributed in the hope that it will be       ////
30//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32//// PURPOSE.  See the GNU Lesser General Public License for more ////
33//// details.                                                     ////
34////                                                              ////
35//// You should have received a copy of the GNU Lesser General    ////
36//// Public License along with this source; if not, download it   ////
37//// from http://www.opencores.org/lgpl.shtml                     ////
38////                                                              ////
39//////////////////////////////////////////////////////////////////////
40//
41// CVS Revision History
42//
43// $Log: not supported by cvs2svn $
44// Revision 1.5  2002/08/14 18:16:59  mohor
45// LinkFail signal was not latching appropriate bit.
46//
47// Revision 1.4  2002/03/02 21:06:01  mohor
48// LinkFail signal was not latching appropriate bit.
49//
50// Revision 1.3  2002/01/23 10:28:16  mohor
51// Link in the header changed.
52//
53// Revision 1.2  2001/10/19 08:43:51  mohor
54// eth_timescale.v changed to timescale.v This is done because of the
55// simulation of the few cores in a one joined project.
56//
57// Revision 1.1  2001/08/06 14:44:29  mohor
58// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
59// Include files fixed to contain no path.
60// File names and module names changed ta have a eth_ prologue in the name.
61// File eth_timescale.v is used to define timescale
62// All pin names on the top module are changed to contain _I, _O or _OE at the end.
63// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
64// and Mdo_OE. The bidirectional signal must be created on the top level. This
65// is done due to the ASIC tools.
66//
67// Revision 1.1  2001/07/30 21:23:42  mohor
68// Directory structure changed. Files checked and joind together.
69//
70// Revision 1.3  2001/06/01 22:28:56  mohor
71// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
72//
73//
74
75`include "timescale.v"
76
77
78module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, 
79                    LatchByte, ShiftedBit, Prsd, LinkFail);
80
81
82parameter Tp=1;
83
84input       Clk;              // Input clock (Host clock)
85input       Reset;            // Reset signal
86input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
87input       Mdi;              // MII input data
88input [4:0] Fiad;             // PHY address
89input [4:0] Rgad;             // Register address (within the selected PHY)
90input [15:0]CtrlData;         // Control data (data to be written to the PHY)
91input       WriteOp;          // The current operation is a PHY register write operation
92input [3:0] ByteSelect;       // Byte select
93input [1:0] LatchByte;        // Byte select for latching (read operation)
94
95output      ShiftedBit;       // Bit shifted out of the shift register
96output[15:0]Prsd;             // Read Status Data (data read from the PHY)
97output      LinkFail;         // Link Integrity Signal
98
99reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
100reg   [15:0]Prsd;
101reg         LinkFail;
102
103
104
105
106// ShiftReg[7:0] :: Shift Register Data
107always @ (posedge Clk or posedge Reset) 
108begin
109  if(Reset)
110    begin
111      ShiftReg[7:0] <= #Tp 8'h0;
112      Prsd[15:0] <= #Tp 16'h0;
113      LinkFail <= #Tp 1'b0;
114    end
115  else
116    begin
117      if(MdcEn_n)
118        begin 
119          if(|ByteSelect)
120            begin
121              case (ByteSelect[3:0])  // synopsys parallel_case full_case
122                4'h1 :    ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
123                4'h2 :    ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
124                4'h4 :    ShiftReg[7:0] <= #Tp CtrlData[15:8];
125                4'h8 :    ShiftReg[7:0] <= #Tp CtrlData[7:0];
126              endcase
127            end 
128          else
129            begin
130              ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
131              if(LatchByte[0])
132                begin
133                  Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
134                  if(Rgad == 5'h01)
135                    LinkFail <= #Tp ~ShiftReg[1];  // this is bit [2], because it is not shifted yet
136                end
137              else
138                begin
139                  if(LatchByte[1])
140                    Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
141                end
142            end
143        end
144    end
145end
146
147
148assign ShiftedBit = ShiftReg[7];
149
150
151endmodule
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